Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/PS2_module.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/SERIAL_module.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/SOUND_module.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/SPI_module.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/TIMER_module.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/gowin_clkdiv/gowin_clkdiv.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/gowin_dpb/gowin_dpb.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/gowin_rpll/gowin_rpll.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/hdmi/svo_defines.vh /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/hdmi/svo_enc.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/hdmi/svo_openldi.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/hdmi/svo_tcard.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/hdmi/svo_term.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/hdmi/svo_tmds.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/hdmi/svo_utils.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/hdmi/svo_vdma.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/svo_hdmi.v /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/termfont_new.vh /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/termfont_old.vh /home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.01 Education |
| Part Number | GW1NR-LV9QN88PC6/I5 |
| Device | GW1NR-9 |
| Device Version | C |
| Created Time | Fri Oct 3 17:03:25 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 445.762MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.087s, Elapsed time = 0h 0m 0.086s, Peak memory usage = 445.762MB Optimizing Phase 1: CPU time = 0h 0m 0.02s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 445.762MB Optimizing Phase 2: CPU time = 0h 0m 0.084s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 445.762MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.023s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 445.762MB Inferring Phase 1: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 445.762MB Inferring Phase 2: CPU time = 0h 0m 0.004s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 445.762MB Inferring Phase 3: CPU time = 0h 0m 0.007s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 445.762MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.088s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 445.762MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.014s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 445.762MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.012s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 445.762MB Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 445.762MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.178s, Elapsed time = 0h 0m 0.177s, Peak memory usage = 445.762MB Generate output files: CPU time = 0h 0m 0.074s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 445.762MB |
| Total Time and Memory Usage | CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 445.762MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 46 |
| I/O Buf | 42 |
| IBUF | 13 |
| OBUF | 15 |
| IOBUF | 10 |
| ELVDS_OBUF | 4 |
| Register | 1054 |
| DFF | 40 |
| DFFE | 378 |
| DFFS | 2 |
| DFFSE | 25 |
| DFFR | 158 |
| DFFRE | 447 |
| DFFC | 4 |
| LUT | 1542 |
| LUT2 | 200 |
| LUT3 | 496 |
| LUT4 | 844 |
| LUT5 | 2 |
| MUX | 144 |
| MUX2 | 144 |
| ALU | 361 |
| ALU | 361 |
| SSRAM | 13 |
| RAM16S4 | 9 |
| RAM16SDP4 | 4 |
| INV | 26 |
| INV | 26 |
| IOLOGIC | 3 |
| OSER10 | 3 |
| BSRAM | 20 |
| DPB | 19 |
| pROM | 1 |
| CLOCK | 2 |
| CLKDIV | 1 |
| rPLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2153(1714 LUT, 361 ALU, 13 RAM16) / 8640 | 25% |
| Register | 1054 / 6693 | 16% |
| --Register as Latch | 0 / 6693 | 0% |
| --Register as FF | 1054 / 6693 | 16% |
| BSRAM | 20 / 26 | 77% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 37.037 | 27.000 | 0.000 | 18.519 | clk_ibuf/I | ||
| 2 | cpuclk | Base | 20.000 | 50.000 | 0.000 | 10.000 | cpuclk_ibuf/I | ||
| 3 | svo_hdmi_inst/svo_tcard/bram_aclock | Base | 20.000 | 50.000 | 0.000 | 10.000 | svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q | ||
| 4 | test1/wng1/fsr_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | test1/wng1/fsr_clk_s0/Q | ||
| 5 | u_pll/rpll_inst/CLKOUT.default_gen_clk | Generated | 7.937 | 126.000 | 0.000 | 3.968 | clk_ibuf/I | clk | u_pll/rpll_inst/CLKOUT |
| 6 | u_pll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 7.937 | 126.000 | 0.000 | 3.968 | clk_ibuf/I | clk | u_pll/rpll_inst/CLKOUTP |
| 7 | u_pll/rpll_inst/CLKOUTD.default_gen_clk | Generated | 15.873 | 63.000 | 0.000 | 7.937 | clk_ibuf/I | clk | u_pll/rpll_inst/CLKOUTD |
| 8 | u_pll/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 23.810 | 42.000 | 0.000 | 11.905 | clk_ibuf/I | clk | u_pll/rpll_inst/CLKOUTD3 |
| 9 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 39.683 | 25.200 | 0.000 | 19.841 | u_pll/rpll_inst/CLKOUT | u_pll/rpll_inst/CLKOUT.default_gen_clk | u_div_5/clkdiv_inst/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | cpuclk | 50.000(MHz) | 24.142(MHz) | 25 | TOP |
| 2 | test1/wng1/fsr_clk | 50.000(MHz) | 257.909(MHz) | 2 | TOP |
| 3 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | 25.200(MHz) | 30.672(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -21.422 |
| Data Arrival Time | 41.748 |
| Data Required Time | 20.326 |
| From | test1/env1/env_amp_0_s0 |
| To | test1/dac1/outshr_10_s0 |
| Launch Clk | cpuclk[R] |
| Latch Clk | cpuclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | cpuclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 562 | cpuclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | test1/env1/env_amp_0_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 11 | test1/env1/env_amp_0_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | test1/w001_6_s3/I1 |
| 3.243 | 1.099 | tINS | FF | 1 | test1/w001_6_s3/F |
| 4.203 | 0.960 | tNET | FF | 1 | test1/w001_6_s1/I1 |
| 5.302 | 1.099 | tINS | FF | 2 | test1/w001_6_s1/F |
| 6.262 | 0.960 | tNET | FF | 1 | test1/w001_6_s0/I2 |
| 7.084 | 0.822 | tINS | FF | 2 | test1/w001_6_s0/F |
| 8.044 | 0.960 | tNET | FF | 2 | test1/n376_s/I0 |
| 9.027 | 0.983 | tINS | FF | 1 | test1/n376_s/SUM |
| 9.987 | 0.960 | tNET | FF | 1 | test1/w002_6_s5/I1 |
| 11.086 | 1.099 | tINS | FF | 1 | test1/w002_6_s5/F |
| 12.046 | 0.960 | tNET | FF | 1 | test1/w002_6_s2/I2 |
| 12.868 | 0.822 | tINS | FF | 3 | test1/w002_6_s2/F |
| 13.828 | 0.960 | tNET | FF | 1 | test1/w002_6_s6/I3 |
| 14.454 | 0.626 | tINS | FF | 2 | test1/w002_6_s6/F |
| 15.414 | 0.960 | tNET | FF | 2 | test1/n552_s/I0 |
| 16.372 | 0.958 | tINS | FF | 1 | test1/n552_s/COUT |
| 16.372 | 0.000 | tNET | FF | 2 | test1/n551_s/CIN |
| 16.935 | 0.563 | tINS | FF | 2 | test1/n551_s/SUM |
| 17.895 | 0.960 | tNET | FF | 1 | test1/w003_7_s4/I1 |
| 18.994 | 1.099 | tINS | FF | 1 | test1/w003_7_s4/F |
| 19.954 | 0.960 | tNET | FF | 1 | test1/w003_7_s1/I3 |
| 20.580 | 0.626 | tINS | FF | 1 | test1/w003_7_s1/F |
| 21.540 | 0.960 | tNET | FF | 1 | test1/w003_7_s0/I2 |
| 22.362 | 0.822 | tINS | FF | 2 | test1/w003_7_s0/F |
| 23.322 | 0.960 | tNET | FF | 2 | test1/n669_1_s/I0 |
| 24.280 | 0.958 | tINS | FF | 1 | test1/n669_1_s/COUT |
| 24.280 | 0.000 | tNET | FF | 2 | test1/n668_1_s/CIN |
| 24.843 | 0.563 | tINS | FF | 1 | test1/n668_1_s/SUM |
| 25.803 | 0.960 | tNET | FF | 1 | test1/w004_8_s2/I2 |
| 26.625 | 0.822 | tINS | FF | 2 | test1/w004_8_s2/F |
| 27.585 | 0.960 | tNET | FF | 1 | test1/w004_8_s0/I2 |
| 28.407 | 0.822 | tINS | FF | 1 | test1/w004_8_s0/F |
| 29.367 | 0.960 | tNET | FF | 2 | test1/n702_1_s/I0 |
| 30.325 | 0.958 | tINS | FF | 1 | test1/n702_1_s/COUT |
| 30.325 | 0.000 | tNET | FF | 2 | test1/n701_1_s/CIN |
| 30.888 | 0.563 | tINS | FF | 2 | test1/n701_1_s/SUM |
| 31.848 | 0.960 | tNET | FF | 1 | test1/w005_9_s2/I2 |
| 32.670 | 0.822 | tINS | FF | 1 | test1/w005_9_s2/F |
| 33.630 | 0.960 | tNET | FF | 1 | test1/w005_9_s0/I3 |
| 34.256 | 0.626 | tINS | FF | 1 | test1/w005_9_s0/F |
| 35.216 | 0.960 | tNET | FF | 2 | test1/n735_1_s/I0 |
| 36.174 | 0.958 | tINS | FF | 1 | test1/n735_1_s/COUT |
| 36.174 | 0.000 | tNET | FF | 2 | test1/n734_1_s/CIN |
| 36.737 | 0.563 | tINS | FF | 1 | test1/n734_1_s/SUM |
| 37.697 | 0.960 | tNET | FF | 1 | test1/dac1/n19_s5/I1 |
| 38.796 | 1.099 | tINS | FF | 1 | test1/dac1/n19_s5/F |
| 39.756 | 0.960 | tNET | FF | 1 | test1/dac1/n19_s0/I0 |
| 40.788 | 1.032 | tINS | FF | 1 | test1/dac1/n19_s0/F |
| 41.748 | 0.960 | tNET | FF | 1 | test1/dac1/outshr_10_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | cpuclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 562 | cpuclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | test1/dac1/outshr_10_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | test1/dac1/outshr_10_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 25 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 20.404, 49.739%; route: 20.160, 49.144%; tC2Q: 0.458, 1.117% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:| Slack | -20.817 |
| Data Arrival Time | 41.143 |
| Data Required Time | 20.326 |
| From | test1/env1/env_amp_0_s0 |
| To | test1/dac1/outshr_9_s0 |
| Launch Clk | cpuclk[R] |
| Latch Clk | cpuclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | cpuclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 562 | cpuclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | test1/env1/env_amp_0_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 11 | test1/env1/env_amp_0_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | test1/w001_6_s3/I1 |
| 3.243 | 1.099 | tINS | FF | 1 | test1/w001_6_s3/F |
| 4.203 | 0.960 | tNET | FF | 1 | test1/w001_6_s1/I1 |
| 5.302 | 1.099 | tINS | FF | 2 | test1/w001_6_s1/F |
| 6.262 | 0.960 | tNET | FF | 1 | test1/w001_6_s0/I2 |
| 7.084 | 0.822 | tINS | FF | 2 | test1/w001_6_s0/F |
| 8.044 | 0.960 | tNET | FF | 2 | test1/n376_s/I0 |
| 9.027 | 0.983 | tINS | FF | 1 | test1/n376_s/SUM |
| 9.987 | 0.960 | tNET | FF | 1 | test1/w002_6_s5/I1 |
| 11.086 | 1.099 | tINS | FF | 1 | test1/w002_6_s5/F |
| 12.046 | 0.960 | tNET | FF | 1 | test1/w002_6_s2/I2 |
| 12.868 | 0.822 | tINS | FF | 3 | test1/w002_6_s2/F |
| 13.828 | 0.960 | tNET | FF | 1 | test1/w002_6_s6/I3 |
| 14.454 | 0.626 | tINS | FF | 2 | test1/w002_6_s6/F |
| 15.414 | 0.960 | tNET | FF | 2 | test1/n552_s/I0 |
| 16.372 | 0.958 | tINS | FF | 1 | test1/n552_s/COUT |
| 16.372 | 0.000 | tNET | FF | 2 | test1/n551_s/CIN |
| 16.935 | 0.563 | tINS | FF | 2 | test1/n551_s/SUM |
| 17.895 | 0.960 | tNET | FF | 1 | test1/w003_7_s4/I1 |
| 18.994 | 1.099 | tINS | FF | 1 | test1/w003_7_s4/F |
| 19.954 | 0.960 | tNET | FF | 1 | test1/w003_7_s1/I3 |
| 20.580 | 0.626 | tINS | FF | 1 | test1/w003_7_s1/F |
| 21.540 | 0.960 | tNET | FF | 1 | test1/w003_7_s0/I2 |
| 22.362 | 0.822 | tINS | FF | 2 | test1/w003_7_s0/F |
| 23.322 | 0.960 | tNET | FF | 2 | test1/n669_1_s/I0 |
| 24.280 | 0.958 | tINS | FF | 1 | test1/n669_1_s/COUT |
| 24.280 | 0.000 | tNET | FF | 2 | test1/n668_1_s/CIN |
| 24.843 | 0.563 | tINS | FF | 1 | test1/n668_1_s/SUM |
| 25.803 | 0.960 | tNET | FF | 1 | test1/w004_8_s2/I2 |
| 26.625 | 0.822 | tINS | FF | 2 | test1/w004_8_s2/F |
| 27.585 | 0.960 | tNET | FF | 1 | test1/w004_8_s0/I2 |
| 28.407 | 0.822 | tINS | FF | 1 | test1/w004_8_s0/F |
| 29.367 | 0.960 | tNET | FF | 2 | test1/n702_1_s/I0 |
| 30.325 | 0.958 | tINS | FF | 1 | test1/n702_1_s/COUT |
| 30.325 | 0.000 | tNET | FF | 2 | test1/n701_1_s/CIN |
| 30.888 | 0.563 | tINS | FF | 2 | test1/n701_1_s/SUM |
| 31.848 | 0.960 | tNET | FF | 1 | test1/w005_9_s2/I2 |
| 32.670 | 0.822 | tINS | FF | 1 | test1/w005_9_s2/F |
| 33.630 | 0.960 | tNET | FF | 1 | test1/w005_9_s0/I3 |
| 34.256 | 0.626 | tINS | FF | 1 | test1/w005_9_s0/F |
| 35.216 | 0.960 | tNET | FF | 2 | test1/n735_1_s/I0 |
| 36.199 | 0.983 | tINS | FF | 1 | test1/n735_1_s/SUM |
| 37.159 | 0.960 | tNET | FF | 1 | test1/dac1/n20_s3/I0 |
| 38.191 | 1.032 | tINS | FF | 1 | test1/dac1/n20_s3/F |
| 39.151 | 0.960 | tNET | FF | 1 | test1/dac1/n20_s0/I0 |
| 40.183 | 1.032 | tINS | FF | 1 | test1/dac1/n20_s0/F |
| 41.143 | 0.960 | tNET | FF | 1 | test1/dac1/outshr_9_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | cpuclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 562 | cpuclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | test1/dac1/outshr_9_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | test1/dac1/outshr_9_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 24 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 19.799, 48.986%; route: 20.160, 49.880%; tC2Q: 0.458, 1.134% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:| Slack | -19.734 |
| Data Arrival Time | 40.060 |
| Data Required Time | 20.326 |
| From | test1/env1/env_amp_1_s0 |
| To | test1/dac1/outshr_11_s0 |
| Launch Clk | cpuclk[R] |
| Latch Clk | cpuclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | cpuclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 562 | cpuclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | test1/env1/env_amp_1_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 12 | test1/env1/env_amp_1_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | test1/ampA_1_s0/I1 |
| 3.243 | 1.099 | tINS | FF | 4 | test1/ampA_1_s0/F |
| 4.203 | 0.960 | tNET | FF | 1 | test1/w001_11_s1/I1 |
| 5.302 | 1.099 | tINS | FF | 5 | test1/w001_11_s1/F |
| 6.262 | 0.960 | tNET | FF | 1 | test1/w001_8_s2/I0 |
| 7.294 | 1.032 | tINS | FF | 3 | test1/w001_8_s2/F |
| 8.254 | 0.960 | tNET | FF | 1 | test1/w001_8_s7/I3 |
| 8.880 | 0.626 | tINS | FF | 2 | test1/w001_8_s7/F |
| 9.840 | 0.960 | tNET | FF | 2 | test1/n374_s/I0 |
| 10.798 | 0.958 | tINS | FF | 1 | test1/n374_s/COUT |
| 10.798 | 0.000 | tNET | FF | 2 | test1/n373_s/CIN |
| 10.855 | 0.057 | tINS | FF | 1 | test1/n373_s/COUT |
| 10.855 | 0.000 | tNET | FF | 2 | test1/n372_s/CIN |
| 11.418 | 0.563 | tINS | FF | 2 | test1/n372_s/SUM |
| 12.378 | 0.960 | tNET | FF | 1 | test1/w002_10_s2/I1 |
| 13.477 | 1.099 | tINS | FF | 2 | test1/w002_10_s2/F |
| 14.437 | 0.960 | tNET | FF | 1 | test1/w002_10_s3/I3 |
| 15.063 | 0.626 | tINS | FF | 1 | test1/w002_10_s3/F |
| 16.023 | 0.960 | tNET | FF | 1 | test1/w002_10_s0/I2 |
| 16.845 | 0.822 | tINS | FF | 2 | test1/w002_10_s0/F |
| 17.805 | 0.960 | tNET | FF | 2 | test1/n548_s/I0 |
| 18.788 | 0.983 | tINS | FF | 2 | test1/n548_s/SUM |
| 19.748 | 0.960 | tNET | FF | 1 | test1/w003_10_s5/I2 |
| 20.570 | 0.822 | tINS | FF | 2 | test1/w003_10_s5/F |
| 21.530 | 0.960 | tNET | FF | 1 | test1/w003_10_s4/I3 |
| 22.156 | 0.626 | tINS | FF | 1 | test1/w003_10_s4/F |
| 23.116 | 0.960 | tNET | FF | 1 | test1/w003_10_s2/I3 |
| 23.742 | 0.626 | tINS | FF | 3 | test1/w003_10_s2/F |
| 24.702 | 0.960 | tNET | FF | 1 | test1/w003_10_s8/I3 |
| 25.328 | 0.626 | tINS | FF | 1 | test1/w003_10_s8/F |
| 26.288 | 0.960 | tNET | FF | 2 | test1/n666_1_s/I0 |
| 27.271 | 0.983 | tINS | FF | 2 | test1/n666_1_s/SUM |
| 28.231 | 0.960 | tNET | FF | 1 | test1/w004_10_s0/I2 |
| 29.053 | 0.822 | tINS | FF | 1 | test1/w004_10_s0/F |
| 30.013 | 0.960 | tNET | FF | 2 | test1/n700_1_s/I0 |
| 30.996 | 0.983 | tINS | FF | 1 | test1/n700_1_s/SUM |
| 31.956 | 0.960 | tNET | FF | 1 | test1/w005_10_s2/I2 |
| 32.778 | 0.822 | tINS | FF | 2 | test1/w005_10_s2/F |
| 33.738 | 0.960 | tNET | FF | 1 | test1/w005_10_s0/I2 |
| 34.560 | 0.822 | tINS | FF | 1 | test1/w005_10_s0/F |
| 35.520 | 0.960 | tNET | FF | 2 | test1/n734_1_s/I0 |
| 36.478 | 0.958 | tINS | FF | 1 | test1/n734_1_s/COUT |
| 36.478 | 0.000 | tNET | FF | 2 | test1/n733_1_s/CIN |
| 37.041 | 0.563 | tINS | FF | 1 | test1/n733_1_s/SUM |
| 38.001 | 0.960 | tNET | FF | 1 | test1/dac1/n18_s1/I1 |
| 39.100 | 1.099 | tINS | FF | 1 | test1/dac1/n18_s1/F |
| 40.060 | 0.960 | tNET | FF | 1 | test1/dac1/outshr_11_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | cpuclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 562 | cpuclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | test1/dac1/outshr_11_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | test1/dac1/outshr_11_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 23 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 18.716, 47.582%; route: 20.160, 51.253%; tC2Q: 0.458, 1.165% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:| Slack | -18.970 |
| Data Arrival Time | 39.296 |
| Data Required Time | 20.326 |
| From | test1/env1/env_amp_0_s0 |
| To | test1/dac1/outshr_8_s0 |
| Launch Clk | cpuclk[R] |
| Latch Clk | cpuclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | cpuclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 562 | cpuclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | test1/env1/env_amp_0_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 11 | test1/env1/env_amp_0_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | test1/w001_6_s3/I1 |
| 3.243 | 1.099 | tINS | FF | 1 | test1/w001_6_s3/F |
| 4.203 | 0.960 | tNET | FF | 1 | test1/w001_6_s1/I1 |
| 5.302 | 1.099 | tINS | FF | 2 | test1/w001_6_s1/F |
| 6.262 | 0.960 | tNET | FF | 1 | test1/w001_6_s0/I2 |
| 7.084 | 0.822 | tINS | FF | 2 | test1/w001_6_s0/F |
| 8.044 | 0.960 | tNET | FF | 2 | test1/n376_s/I0 |
| 9.027 | 0.983 | tINS | FF | 1 | test1/n376_s/SUM |
| 9.987 | 0.960 | tNET | FF | 1 | test1/w002_6_s5/I1 |
| 11.086 | 1.099 | tINS | FF | 1 | test1/w002_6_s5/F |
| 12.046 | 0.960 | tNET | FF | 1 | test1/w002_6_s2/I2 |
| 12.868 | 0.822 | tINS | FF | 3 | test1/w002_6_s2/F |
| 13.828 | 0.960 | tNET | FF | 1 | test1/w002_6_s6/I3 |
| 14.454 | 0.626 | tINS | FF | 2 | test1/w002_6_s6/F |
| 15.414 | 0.960 | tNET | FF | 2 | test1/n552_s/I0 |
| 16.372 | 0.958 | tINS | FF | 1 | test1/n552_s/COUT |
| 16.372 | 0.000 | tNET | FF | 2 | test1/n551_s/CIN |
| 16.935 | 0.563 | tINS | FF | 2 | test1/n551_s/SUM |
| 17.895 | 0.960 | tNET | FF | 1 | test1/w003_7_s4/I1 |
| 18.994 | 1.099 | tINS | FF | 1 | test1/w003_7_s4/F |
| 19.954 | 0.960 | tNET | FF | 1 | test1/w003_7_s1/I3 |
| 20.580 | 0.626 | tINS | FF | 1 | test1/w003_7_s1/F |
| 21.540 | 0.960 | tNET | FF | 1 | test1/w003_7_s0/I2 |
| 22.362 | 0.822 | tINS | FF | 2 | test1/w003_7_s0/F |
| 23.322 | 0.960 | tNET | FF | 2 | test1/n669_1_s/I0 |
| 24.280 | 0.958 | tINS | FF | 1 | test1/n669_1_s/COUT |
| 24.280 | 0.000 | tNET | FF | 2 | test1/n668_1_s/CIN |
| 24.843 | 0.563 | tINS | FF | 1 | test1/n668_1_s/SUM |
| 25.803 | 0.960 | tNET | FF | 1 | test1/w004_8_s2/I2 |
| 26.625 | 0.822 | tINS | FF | 2 | test1/w004_8_s2/F |
| 27.585 | 0.960 | tNET | FF | 1 | test1/w004_8_s0/I2 |
| 28.407 | 0.822 | tINS | FF | 1 | test1/w004_8_s0/F |
| 29.367 | 0.960 | tNET | FF | 2 | test1/n702_1_s/I0 |
| 30.350 | 0.983 | tINS | FF | 2 | test1/n702_1_s/SUM |
| 31.310 | 0.960 | tNET | FF | 1 | test1/w005_8_s2/I1 |
| 32.409 | 1.099 | tINS | FF | 1 | test1/w005_8_s2/F |
| 33.369 | 0.960 | tNET | FF | 2 | test1/n736_1_s/I0 |
| 34.352 | 0.983 | tINS | FF | 1 | test1/n736_1_s/SUM |
| 35.312 | 0.960 | tNET | FF | 1 | test1/dac1/n21_s3/I0 |
| 36.344 | 1.032 | tINS | FF | 1 | test1/dac1/n21_s3/F |
| 37.304 | 0.960 | tNET | FF | 1 | test1/dac1/n21_s0/I0 |
| 38.336 | 1.032 | tINS | FF | 1 | test1/dac1/n21_s0/F |
| 39.296 | 0.960 | tNET | FF | 1 | test1/dac1/outshr_8_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | cpuclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 562 | cpuclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | test1/dac1/outshr_8_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | test1/dac1/outshr_8_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 22 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 18.912, 49.033%; route: 19.200, 49.779%; tC2Q: 0.458, 1.188% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:| Slack | -17.190 |
| Data Arrival Time | 37.516 |
| Data Required Time | 20.326 |
| From | test1/env1/env_amp_0_s0 |
| To | test1/dac1/outshr_7_s0 |
| Launch Clk | cpuclk[R] |
| Latch Clk | cpuclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | cpuclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 562 | cpuclk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | test1/env1/env_amp_0_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 11 | test1/env1/env_amp_0_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | test1/w001_6_s3/I1 |
| 3.243 | 1.099 | tINS | FF | 1 | test1/w001_6_s3/F |
| 4.203 | 0.960 | tNET | FF | 1 | test1/w001_6_s1/I1 |
| 5.302 | 1.099 | tINS | FF | 2 | test1/w001_6_s1/F |
| 6.262 | 0.960 | tNET | FF | 1 | test1/w001_6_s0/I2 |
| 7.084 | 0.822 | tINS | FF | 2 | test1/w001_6_s0/F |
| 8.044 | 0.960 | tNET | FF | 2 | test1/n376_s/I0 |
| 9.027 | 0.983 | tINS | FF | 1 | test1/n376_s/SUM |
| 9.987 | 0.960 | tNET | FF | 1 | test1/w002_6_s5/I1 |
| 11.086 | 1.099 | tINS | FF | 1 | test1/w002_6_s5/F |
| 12.046 | 0.960 | tNET | FF | 1 | test1/w002_6_s2/I2 |
| 12.868 | 0.822 | tINS | FF | 3 | test1/w002_6_s2/F |
| 13.828 | 0.960 | tNET | FF | 1 | test1/w002_6_s6/I3 |
| 14.454 | 0.626 | tINS | FF | 2 | test1/w002_6_s6/F |
| 15.414 | 0.960 | tNET | FF | 2 | test1/n552_s/I0 |
| 16.397 | 0.983 | tINS | FF | 1 | test1/n552_s/SUM |
| 17.357 | 0.960 | tNET | FF | 1 | test1/w003_6_s6/I1 |
| 18.456 | 1.099 | tINS | FF | 3 | test1/w003_6_s6/F |
| 19.416 | 0.960 | tNET | FF | 1 | test1/w003_6_s0/I2 |
| 20.238 | 0.822 | tINS | FF | 1 | test1/w003_6_s0/F |
| 21.198 | 0.960 | tNET | FF | 2 | test1/n670_1_s/I0 |
| 22.181 | 0.983 | tINS | FF | 2 | test1/n670_1_s/SUM |
| 23.141 | 0.960 | tNET | FF | 1 | test1/w004_6_s6/I1 |
| 24.240 | 1.099 | tINS | FF | 1 | test1/w004_6_s6/F |
| 25.200 | 0.960 | tNET | FF | 2 | test1/n704_1_s/I0 |
| 26.183 | 0.983 | tINS | FF | 1 | test1/n704_1_s/SUM |
| 27.143 | 0.960 | tNET | FF | 1 | test1/w005_6_s4/I0 |
| 28.175 | 1.032 | tINS | FF | 2 | test1/w005_6_s4/F |
| 29.135 | 0.960 | tNET | FF | 1 | test1/w005_6_s0/I2 |
| 29.957 | 0.822 | tINS | FF | 1 | test1/w005_6_s0/F |
| 30.917 | 0.960 | tNET | FF | 2 | test1/n738_1_s/I0 |
| 31.875 | 0.958 | tINS | FF | 1 | test1/n738_1_s/COUT |
| 31.875 | 0.000 | tNET | FF | 2 | test1/n737_1_s/CIN |
| 32.438 | 0.563 | tINS | FF | 1 | test1/n737_1_s/SUM |
| 33.398 | 0.960 | tNET | FF | 1 | test1/dac1/n22_s1/I1 |
| 34.497 | 1.099 | tINS | FF | 1 | test1/dac1/n22_s1/F |
| 35.457 | 0.960 | tNET | FF | 1 | test1/dac1/n22_s0/I1 |
| 36.556 | 1.099 | tINS | FF | 1 | test1/dac1/n22_s0/F |
| 37.516 | 0.960 | tNET | FF | 1 | test1/dac1/outshr_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | cpuclk | |||
| 20.000 | 0.000 | tCL | RR | 1 | cpuclk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 562 | cpuclk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | test1/dac1/outshr_7_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | test1/dac1/outshr_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 20 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 18.092, 49.176%; route: 18.240, 49.578%; tC2Q: 0.458, 1.246% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |