Timing Messages

Report Title	Timing Analysis Report
Design File	/home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/impl/gwsynthesis/hdmi.vg
Physical Constraints File	/home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/hdmi.cst
Timing Constraint File	/home/milton/kraft80/hardware/TANG-NANO-VIDEO/hdmi/src/hdmi.sdc
Tool Version	V1.9.11.01 Education
Part Number	GW1NR-LV9QN88PC6/I5
Device	GW1NR-9
Device Version	C
Created Time	Fri Oct 3 17:03:28 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	7414
Numbers of Endpoints Analyzed	3573
Numbers of Falling Endpoints	564
Numbers of Setup Violated Endpoints	9
Numbers of Hold Violated Endpoints	1

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk_osc	Base	37.037	27.000	0.000	18.518			clk
2	cpuclk	Base	20.000	50.000	0.000	10.000			cpuclk_ibuf/I
3	test1/wng1/fsr_clk	Base	20.000	50.000	0.000	10.000			test1/wng1/fsr_clk_s0/Q
4	svo_hdmi_inst/svo_tcard/bram_aclock	Base	20.000	50.000	0.000	10.000			svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
5	u_pll/rpll_inst/CLKOUT.default_gen_clk	Generated	7.936	126.000	0.000	3.968	clk_ibuf/I	clk_osc	u_pll/rpll_inst/CLKOUT
6	u_pll/rpll_inst/CLKOUTP.default_gen_clk	Generated	7.936	126.000	0.000	3.968	clk_ibuf/I	clk_osc	u_pll/rpll_inst/CLKOUTP
7	u_pll/rpll_inst/CLKOUTD.default_gen_clk	Generated	15.873	63.000	0.000	7.936	clk_ibuf/I	clk_osc	u_pll/rpll_inst/CLKOUTD
8	u_pll/rpll_inst/CLKOUTD3.default_gen_clk	Generated	23.809	42.000	0.000	11.905	clk_ibuf/I	clk_osc	u_pll/rpll_inst/CLKOUTD3
9	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	Generated	39.682	25.200	0.000	19.841	u_pll/rpll_inst/CLKOUT	u_pll/rpll_inst/CLKOUT.default_gen_clk	u_div_5/clkdiv_inst/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	cpuclk	50.000(MHz)	30.770(MHz)	22	TOP
2	test1/wng1/fsr_clk	50.000(MHz)	436.063(MHz)	2	TOP
3	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	25.200(MHz)	27.456(MHz)	10	TOP

No timing paths to get frequency of clk_osc!

No timing paths to get frequency of svo_hdmi_inst/svo_tcard/bram_aclock!

No timing paths to get frequency of u_pll/rpll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of u_pll/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of u_pll/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of u_pll/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk_osc	Setup	0.000	0
clk_osc	Hold	0.000	0
cpuclk	Setup	-65.129	7
cpuclk	Hold	0.000	0
test1/wng1/fsr_clk	Setup	0.000	0
test1/wng1/fsr_clk	Hold	0.000	0
svo_hdmi_inst/svo_tcard/bram_aclock	Setup	0.000	0
svo_hdmi_inst/svo_tcard/bram_aclock	Hold	0.000	0
u_pll/rpll_inst/CLKOUT.default_gen_clk	Setup	0.000	0
u_pll/rpll_inst/CLKOUT.default_gen_clk	Hold	0.000	0
u_pll/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
u_pll/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
u_pll/rpll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
u_pll/rpll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
u_pll/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
u_pll/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0
u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	Setup	0.000	0
u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-12.499	test1/env1/env_amp_2_s0/Q	test1/dac1/outshr_10_s0/D	cpuclk:[R]	cpuclk:[R]	20.000	0.000	32.099
2	-12.385	test1/env1/env_amp_2_s0/Q	test1/dac1/outshr_9_s0/D	cpuclk:[R]	cpuclk:[R]	20.000	0.000	31.985
3	-11.835	test1/env1/env_amp_2_s0/Q	test1/dac1/outshr_11_s0/D	cpuclk:[R]	cpuclk:[R]	20.000	0.000	31.435
4	-10.629	test1/toneA/toneout_s23/Q	test1/dac1/outshr_8_s0/D	cpuclk:[R]	cpuclk:[R]	20.000	0.000	30.229
5	-7.602	test1/toneA/toneout_s23/Q	test1/dac1/outshr_7_s0/D	cpuclk:[R]	cpuclk:[R]	20.000	0.000	27.202
6	-6.601	test1/toneA/toneout_s23/Q	test1/dac1/outshr_6_s0/D	cpuclk:[R]	cpuclk:[R]	20.000	0.000	26.201
7	-3.578	test1/env1/env_amp_0_s0/Q	test1/dac1/outshr_5_s0/D	cpuclk:[R]	cpuclk:[R]	20.000	0.000	23.178
8	-0.410	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_0/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	7.374
9	-0.309	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	7.273
10	0.016	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	6.948
11	0.134	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_4/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	6.830
12	0.188	svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_7/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	6.777
13	0.492	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_1/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	6.472
14	0.531	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_5/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	6.433
15	0.881	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_10/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	6.083
16	0.918	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_3/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	6.046
17	0.920	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	6.045
18	1.036	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	5.929
19	1.255	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_17/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	5.709
20	1.279	svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_15/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	5.685
21	1.283	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_13/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	5.681
22	1.284	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_14/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	5.680
23	1.323	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_9/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	5.641
24	1.337	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_2/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	5.628
25	1.432	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_6/CEA	cpuclk:[F]	svo_hdmi_inst/svo_tcard/bram_aclock:[R]	10.000	2.832	5.532

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-0.183	test1/wng1/lfsr1/sfr_1_s0/Q	test1/wng1/noiseout_s0/D	test1/wng1/fsr_clk:[R]	cpuclk:[R]	0.000	-1.444	1.290
2	0.586	svo_hdmi_inst/svo_tmds_2/q_out_0_s0/Q	svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s4/DI[0]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.598
3	0.598	svo_hdmi_inst/svo_term/oresetn_s0/Q	svo_hdmi_inst/svo_term/p1_ypos_6_s0/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.610
4	0.598	svo_hdmi_inst/svo_term/oresetn_s0/Q	svo_hdmi_inst/svo_term/p1_ypos_12_s0/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.610
5	0.708	svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1/Q	svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]	0.000	0.000	0.708
6	0.708	svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0/Q	svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]	0.000	0.000	0.708
7	0.708	svo_hdmi_inst/svo_tcard/grmode1/memcounth_11_s0/Q	svo_hdmi_inst/svo_tcard/grmode1/memcounth_11_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]	0.000	0.000	0.708
8	0.708	svo_hdmi_inst/svo_tcard/txtmode0/cursorcount_0_s1/Q	svo_hdmi_inst/svo_tcard/txtmode0/cursorcount_0_s1/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]	0.000	0.000	0.708
9	0.708	svo_hdmi_inst/svo_tcard/cled4_0_s2/Q	svo_hdmi_inst/svo_tcard/cled4_0_s2/D	cpuclk:[F]	cpuclk:[F]	0.000	0.000	0.708
10	0.708	svo_hdmi_inst/svo_tcard/cled5_0_s2/Q	svo_hdmi_inst/svo_tcard/cled5_0_s2/D	cpuclk:[F]	cpuclk:[F]	0.000	0.000	0.708
11	0.708	svo_hdmi_inst/svo_tcard/counter_0_s0/Q	svo_hdmi_inst/svo_tcard/counter_0_s0/D	cpuclk:[F]	cpuclk:[F]	0.000	0.000	0.708
12	0.708	ps2_1/ps2timeout_0_s1/Q	ps2_1/ps2timeout_0_s1/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708
13	0.708	ps2_1/bitsreceived_3_s0/Q	ps2_1/bitsreceived_3_s0/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708
14	0.708	test1/env1/clkdiv_0_s1/Q	test1/env1/clkdiv_0_s1/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708
15	0.708	test1/wng1/divider_4_s0/Q	test1/wng1/divider_4_s0/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708
16	0.708	test1/wng1/clkdiv_2_s0/Q	test1/wng1/clkdiv_2_s0/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708
17	0.708	test1/wng1/clkdiv_7_s0/Q	test1/wng1/clkdiv_7_s0/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708
18	0.708	test1/toneC/clkdiv_2_s0/Q	test1/toneC/clkdiv_2_s0/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708
19	0.708	test1/toneC/clkdiv_6_s0/Q	test1/toneC/clkdiv_6_s0/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708
20	0.708	test1/toneB/divider_11_s0/Q	test1/toneB/divider_11_s0/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708
21	0.708	test1/toneB/clkdiv_3_s0/Q	test1/toneB/clkdiv_3_s0/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708
22	0.708	test1/toneB/clkdiv_5_s0/Q	test1/toneB/clkdiv_5_s0/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708
23	0.708	test1/toneA/divider_11_s0/Q	test1/toneA/divider_11_s0/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708
24	0.708	test1/toneA/clkdiv_3_s0/Q	test1/toneA/clkdiv_3_s0/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708
25	0.708	test1/toneA/clkdiv_7_s0/Q	test1/toneA/clkdiv_7_s0/D	cpuclk:[R]	cpuclk:[R]	0.000	0.000	0.708

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.975	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[0]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]	3.968	-1.943	4.862
2	0.975	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[1]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]	3.968	-1.943	4.862
3	0.975	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[2]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]	3.968	-1.943	4.862
4	4.936	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[2]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]	7.936	-1.937	4.862
5	4.936	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[1]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]	7.936	-1.937	4.862
6	4.936	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[0]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]	7.936	-1.937	4.862
7	34.775	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[2]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	4.862
8	34.775	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[1]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	4.862
9	34.775	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[0]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	4.862

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.114	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[2]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.965	3.122
2	1.114	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[1]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.965	3.122
3	1.114	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[0]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.965	3.122
4	3.110	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[0]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.122
5	3.110	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[1]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.122
6	3.110	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[2]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.122
7	5.077	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[0]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]	-3.968	-1.971	3.122
8	5.077	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[1]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]	-3.968	-1.971	3.122
9	5.077	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[2]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]	-3.968	-1.971	3.122

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	7.300	8.550	1.250	Low Pulse Width	cpuclk	spi_1/divider_12_s0
2	7.300	8.550	1.250	Low Pulse Width	cpuclk	spi_1/divider_10_s0
3	7.300	8.550	1.250	Low Pulse Width	cpuclk	spi_1/divider_6_s0
4	7.300	8.550	1.250	Low Pulse Width	cpuclk	spi_1/disk_sck_s0
5	7.300	8.550	1.250	Low Pulse Width	cpuclk	spi_1/data_rx_1_s0
6	7.300	8.550	1.250	Low Pulse Width	cpuclk	serial_1/txdata_1_s0
7	7.300	8.550	1.250	Low Pulse Width	cpuclk	test1/r0_4_s0
8	7.300	8.550	1.250	Low Pulse Width	cpuclk	test1/toneB/divider_11_s0
9	7.300	8.550	1.250	Low Pulse Width	cpuclk	svo_hdmi_inst/svo_tcard/bramwraddr_10_s0
10	7.300	8.550	1.250	Low Pulse Width	cpuclk	svo_hdmi_inst/svo_tcard/bramwraddr_11_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-12.499
Data Arrival Time	35.583
Data Required Time	23.084
From	test1/env1/env_amp_2_s0
To	test1/dac1/outshr_10_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
2.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
3.484	1.396	tNET	RR	1	R12C9[0][B]	test1/env1/env_amp_2_s0/CLK
3.942	0.458	tC2Q	RF	10	R12C9[0][B]	test1/env1/env_amp_2_s0/Q
5.760	1.818	tNET	FF	1	R16C14[2][B]	test1/ampA_2_s0/I1
6.386	0.626	tINS	FF	3	R16C14[2][B]	test1/ampA_2_s0/F
7.366	0.980	tNET	FF	1	R18C16[1][B]	test1/w001_11_s1/I0
8.392	1.026	tINS	FR	5	R18C16[1][B]	test1/w001_11_s1/F
8.819	0.427	tNET	RR	1	R17C16[2][A]	test1/w001_8_s2/I0
9.444	0.625	tINS	RR	3	R17C16[2][A]	test1/w001_8_s2/F
9.866	0.423	tNET	RR	1	R18C16[3][A]	test1/w001_8_s7/I3
10.492	0.626	tINS	RF	2	R18C16[3][A]	test1/w001_8_s7/F
11.319	0.826	tNET	FF	2	R18C18[2][A]	test1/n366_1_s/I0
12.277	0.958	tINS	FF	1	R18C18[2][A]	test1/n366_1_s/COUT
12.277	0.000	tNET	FF	2	R18C18[2][B]	test1/n365_1_s/CIN
12.840	0.563	tINS	FF	1	R18C18[2][B]	test1/n365_1_s/SUM
13.330	0.490	tNET	FF	1	R18C16[1][A]	test1/w002_9_s1/I2
14.362	1.032	tINS	FF	1	R18C16[1][A]	test1/w002_9_s1/F
15.166	0.804	tNET	FF	1	R18C13[2][A]	test1/w002_9_s0/I2
16.198	1.032	tINS	FF	5	R18C13[2][A]	test1/w002_9_s0/F
17.498	1.300	tNET	FF	2	R17C10[1][B]	test1/n549_s/I0
18.226	0.728	tINS	FR	3	R17C10[1][B]	test1/n549_s/SUM
18.649	0.423	tNET	RR	1	R17C9[1][B]	test1/w003_9_s5/I1
19.275	0.626	tINS	RF	3	R17C9[1][B]	test1/w003_9_s5/F
20.569	1.294	tNET	FF	1	R18C12[3][A]	test1/w003_9_s0/I2
21.195	0.626	tINS	FF	1	R18C12[3][A]	test1/w003_9_s0/F
21.531	0.336	tNET	FF	2	R18C12[2][B]	test1/n667_1_s/I0
22.525	0.994	tINS	FR	1	R18C12[2][B]	test1/n667_1_s/SUM
22.944	0.419	tNET	RR	1	R18C13[1][A]	test1/w004_9_s2/I2
23.976	1.032	tINS	RF	3	R18C13[1][A]	test1/w004_9_s2/F
25.121	1.144	tNET	FF	1	R20C14[3][B]	test1/w004_9_s0/I2
25.747	0.626	tINS	FF	1	R20C14[3][B]	test1/w004_9_s0/F
26.568	0.821	tNET	FF	2	R18C14[2][B]	test1/n701_1_s/I0
27.551	0.983	tINS	FF	2	R18C14[2][B]	test1/n701_1_s/SUM
28.046	0.496	tNET	FF	1	R20C14[1][A]	test1/w005_9_s2/I2
29.078	1.032	tINS	FF	1	R20C14[1][A]	test1/w005_9_s2/F
29.882	0.804	tNET	FF	1	R17C14[0][B]	test1/w005_9_s0/I3
30.684	0.802	tINS	FR	1	R17C14[0][B]	test1/w005_9_s0/F
31.103	0.419	tNET	RR	2	R17C15[2][B]	test1/n735_1_s/I0
32.061	0.958	tINS	RF	1	R17C15[2][B]	test1/n735_1_s/COUT
32.061	0.000	tNET	FF	2	R17C16[0][A]	test1/n734_1_s/CIN
32.624	0.563	tINS	FF	1	R17C16[0][A]	test1/n734_1_s/SUM
33.913	1.289	tNET	FF	1	R20C15[1][A]	test1/dac1/n19_s5/I1
34.538	0.625	tINS	FR	1	R20C15[1][A]	test1/dac1/n19_s5/F
34.957	0.419	tNET	RR	1	R21C15[0][B]	test1/dac1/n19_s0/I0
35.583	0.626	tINS	RF	1	R21C15[0][B]	test1/dac1/n19_s0/F
35.583	0.000	tNET	FF	1	R21C15[0][B]	test1/dac1/outshr_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cpuclk
20.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
22.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
23.484	1.396	tNET	RR	1	R21C15[0][B]	test1/dac1/outshr_10_s0/CLK
23.084	-0.400	tSu		1	R21C15[0][B]	test1/dac1/outshr_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	22
Arrival Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay	cell: 16.709, 52.055%; route: 14.932, 46.518%; tC2Q: 0.458, 1.428%
Required Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%

Path2

Path Summary:

Slack	-12.385
Data Arrival Time	35.470
Data Required Time	23.084
From	test1/env1/env_amp_2_s0
To	test1/dac1/outshr_9_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
2.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
3.484	1.396	tNET	RR	1	R12C9[0][B]	test1/env1/env_amp_2_s0/CLK
3.942	0.458	tC2Q	RF	10	R12C9[0][B]	test1/env1/env_amp_2_s0/Q
5.760	1.818	tNET	FF	1	R16C14[2][B]	test1/ampA_2_s0/I1
6.386	0.626	tINS	FF	3	R16C14[2][B]	test1/ampA_2_s0/F
7.366	0.980	tNET	FF	1	R18C16[1][B]	test1/w001_11_s1/I0
8.392	1.026	tINS	FR	5	R18C16[1][B]	test1/w001_11_s1/F
8.819	0.427	tNET	RR	1	R17C16[2][A]	test1/w001_8_s2/I0
9.444	0.625	tINS	RR	3	R17C16[2][A]	test1/w001_8_s2/F
9.866	0.423	tNET	RR	1	R18C16[3][A]	test1/w001_8_s7/I3
10.492	0.626	tINS	RF	2	R18C16[3][A]	test1/w001_8_s7/F
11.319	0.826	tNET	FF	2	R18C18[2][A]	test1/n366_1_s/I0
12.277	0.958	tINS	FF	1	R18C18[2][A]	test1/n366_1_s/COUT
12.277	0.000	tNET	FF	2	R18C18[2][B]	test1/n365_1_s/CIN
12.840	0.563	tINS	FF	1	R18C18[2][B]	test1/n365_1_s/SUM
13.330	0.490	tNET	FF	1	R18C16[1][A]	test1/w002_9_s1/I2
14.362	1.032	tINS	FF	1	R18C16[1][A]	test1/w002_9_s1/F
15.166	0.804	tNET	FF	1	R18C13[2][A]	test1/w002_9_s0/I2
16.198	1.032	tINS	FF	5	R18C13[2][A]	test1/w002_9_s0/F
17.498	1.300	tNET	FF	2	R17C10[1][B]	test1/n549_s/I0
18.226	0.728	tINS	FR	3	R17C10[1][B]	test1/n549_s/SUM
18.649	0.423	tNET	RR	1	R17C9[1][B]	test1/w003_9_s5/I1
19.275	0.626	tINS	RF	3	R17C9[1][B]	test1/w003_9_s5/F
20.569	1.294	tNET	FF	1	R18C12[3][A]	test1/w003_9_s0/I2
21.195	0.626	tINS	FF	1	R18C12[3][A]	test1/w003_9_s0/F
21.531	0.336	tNET	FF	2	R18C12[2][B]	test1/n667_1_s/I0
22.525	0.994	tINS	FR	1	R18C12[2][B]	test1/n667_1_s/SUM
22.944	0.419	tNET	RR	1	R18C13[1][A]	test1/w004_9_s2/I2
23.976	1.032	tINS	RF	3	R18C13[1][A]	test1/w004_9_s2/F
25.121	1.144	tNET	FF	1	R20C14[3][B]	test1/w004_9_s0/I2
25.747	0.626	tINS	FF	1	R20C14[3][B]	test1/w004_9_s0/F
26.568	0.821	tNET	FF	2	R18C14[2][B]	test1/n701_1_s/I0
27.551	0.983	tINS	FF	2	R18C14[2][B]	test1/n701_1_s/SUM
28.046	0.496	tNET	FF	1	R20C14[1][A]	test1/w005_9_s2/I2
29.078	1.032	tINS	FF	1	R20C14[1][A]	test1/w005_9_s2/F
29.882	0.804	tNET	FF	1	R17C14[0][B]	test1/w005_9_s0/I3
30.684	0.802	tINS	FR	1	R17C14[0][B]	test1/w005_9_s0/F
31.103	0.419	tNET	RR	2	R17C15[2][B]	test1/n735_1_s/I0
32.086	0.983	tINS	RF	1	R17C15[2][B]	test1/n735_1_s/SUM
32.891	0.804	tNET	FF	1	R20C15[0][A]	test1/dac1/n20_s3/I0
33.952	1.061	tINS	FR	1	R20C15[0][A]	test1/dac1/n20_s3/F
34.371	0.419	tNET	RR	1	R20C14[0][B]	test1/dac1/n20_s0/I0
35.470	1.099	tINS	RF	1	R20C14[0][B]	test1/dac1/n20_s0/F
35.470	0.000	tNET	FF	1	R20C14[0][B]	test1/dac1/outshr_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cpuclk
20.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
22.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
23.484	1.396	tNET	RR	1	R20C14[0][B]	test1/dac1/outshr_9_s0/CLK
23.084	-0.400	tSu		1	R20C14[0][B]	test1/dac1/outshr_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	21
Arrival Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay	cell: 17.080, 53.399%; route: 14.447, 45.168%; tC2Q: 0.458, 1.433%
Required Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%

Path3

Path Summary:

Slack	-11.835
Data Arrival Time	34.919
Data Required Time	23.084
From	test1/env1/env_amp_2_s0
To	test1/dac1/outshr_11_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
2.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
3.484	1.396	tNET	RR	1	R12C9[0][B]	test1/env1/env_amp_2_s0/CLK
3.942	0.458	tC2Q	RF	10	R12C9[0][B]	test1/env1/env_amp_2_s0/Q
5.760	1.818	tNET	FF	1	R16C14[2][B]	test1/ampA_2_s0/I1
6.386	0.626	tINS	FF	3	R16C14[2][B]	test1/ampA_2_s0/F
7.366	0.980	tNET	FF	1	R18C16[1][B]	test1/w001_11_s1/I0
8.392	1.026	tINS	FR	5	R18C16[1][B]	test1/w001_11_s1/F
8.819	0.427	tNET	RR	1	R17C16[2][A]	test1/w001_8_s2/I0
9.444	0.625	tINS	RR	3	R17C16[2][A]	test1/w001_8_s2/F
9.866	0.423	tNET	RR	1	R18C16[3][A]	test1/w001_8_s7/I3
10.492	0.626	tINS	RF	2	R18C16[3][A]	test1/w001_8_s7/F
11.319	0.826	tNET	FF	2	R18C18[2][A]	test1/n366_1_s/I0
12.277	0.958	tINS	FF	1	R18C18[2][A]	test1/n366_1_s/COUT
12.277	0.000	tNET	FF	2	R18C18[2][B]	test1/n365_1_s/CIN
12.840	0.563	tINS	FF	1	R18C18[2][B]	test1/n365_1_s/SUM
13.330	0.490	tNET	FF	1	R18C16[1][A]	test1/w002_9_s1/I2
14.362	1.032	tINS	FF	1	R18C16[1][A]	test1/w002_9_s1/F
15.166	0.804	tNET	FF	1	R18C13[2][A]	test1/w002_9_s0/I2
16.198	1.032	tINS	FF	5	R18C13[2][A]	test1/w002_9_s0/F
17.498	1.300	tNET	FF	2	R17C10[1][B]	test1/n549_s/I0
18.226	0.728	tINS	FR	3	R17C10[1][B]	test1/n549_s/SUM
18.649	0.423	tNET	RR	1	R17C9[1][B]	test1/w003_9_s5/I1
19.275	0.626	tINS	RF	3	R17C9[1][B]	test1/w003_9_s5/F
20.569	1.294	tNET	FF	1	R18C12[3][A]	test1/w003_9_s0/I2
21.195	0.626	tINS	FF	1	R18C12[3][A]	test1/w003_9_s0/F
21.531	0.336	tNET	FF	2	R18C12[2][B]	test1/n667_1_s/I0
22.525	0.994	tINS	FR	1	R18C12[2][B]	test1/n667_1_s/SUM
22.944	0.419	tNET	RR	1	R18C13[1][A]	test1/w004_9_s2/I2
23.976	1.032	tINS	RF	3	R18C13[1][A]	test1/w004_9_s2/F
25.121	1.144	tNET	FF	1	R20C14[3][B]	test1/w004_9_s0/I2
25.747	0.626	tINS	FF	1	R20C14[3][B]	test1/w004_9_s0/F
26.568	0.821	tNET	FF	2	R18C14[2][B]	test1/n701_1_s/I0
27.551	0.983	tINS	FF	2	R18C14[2][B]	test1/n701_1_s/SUM
28.046	0.496	tNET	FF	1	R20C14[1][A]	test1/w005_9_s2/I2
29.078	1.032	tINS	FF	1	R20C14[1][A]	test1/w005_9_s2/F
29.882	0.804	tNET	FF	1	R17C14[0][B]	test1/w005_9_s0/I3
30.684	0.802	tINS	FR	1	R17C14[0][B]	test1/w005_9_s0/F
31.103	0.419	tNET	RR	2	R17C15[2][B]	test1/n735_1_s/I0
32.061	0.958	tINS	RF	1	R17C15[2][B]	test1/n735_1_s/COUT
32.061	0.000	tNET	FF	2	R17C16[0][A]	test1/n734_1_s/CIN
32.118	0.057	tINS	FF	1	R17C16[0][A]	test1/n734_1_s/COUT
32.118	0.000	tNET	FF	2	R17C16[0][B]	test1/n733_1_s/CIN
32.681	0.563	tINS	FF	1	R17C16[0][B]	test1/n733_1_s/SUM
33.820	1.139	tNET	FF	1	R21C15[0][A]	test1/dac1/n18_s1/I1
34.919	1.099	tINS	FF	1	R21C15[0][A]	test1/dac1/n18_s1/F
34.919	0.000	tNET	FF	1	R21C15[0][A]	test1/dac1/outshr_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cpuclk
20.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
22.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
23.484	1.396	tNET	RR	1	R21C15[0][A]	test1/dac1/outshr_11_s0/CLK
23.084	-0.400	tSu		1	R21C15[0][A]	test1/dac1/outshr_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	21
Arrival Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay	cell: 16.614, 52.851%; route: 14.363, 45.691%; tC2Q: 0.458, 1.458%
Required Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%

Path4

Path Summary:

Slack	-10.629
Data Arrival Time	33.713
Data Required Time	23.084
From	test1/toneA/toneout_s23
To	test1/dac1/outshr_8_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
2.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
3.484	1.396	tNET	RR	1	R13C16[1][A]	test1/toneA/toneout_s23/CLK
3.942	0.458	tC2Q	RF	6	R13C16[1][A]	test1/toneA/toneout_s23/Q
5.246	1.304	tNET	FF	1	R17C17[3][A]	test1/w001_6_s2/I0
5.872	0.626	tINS	FF	1	R17C17[3][A]	test1/w001_6_s2/F
7.007	1.135	tNET	FF	1	R16C16[0][B]	test1/w001_6_s1/I0
7.633	0.626	tINS	FF	2	R16C16[0][B]	test1/w001_6_s1/F
8.443	0.810	tNET	FF	1	R17C17[1][B]	test1/w001_6_s0/I2
9.265	0.822	tINS	FF	2	R17C17[1][B]	test1/w001_6_s0/F
9.761	0.496	tNET	FF	2	R18C17[0][A]	test1/n376_s/I0
10.464	0.703	tINS	FF	1	R18C17[0][A]	test1/n376_s/SUM
11.438	0.975	tNET	FF	1	R16C16[0][A]	test1/w002_6_s5/I1
12.064	0.626	tINS	FF	1	R16C16[0][A]	test1/w002_6_s5/F
12.070	0.005	tNET	FF	1	R16C16[1][A]	test1/w002_6_s2/I2
12.696	0.626	tINS	FF	3	R16C16[1][A]	test1/w002_6_s2/F
14.161	1.465	tNET	FF	1	R18C11[2][A]	test1/w002_6_s6/I3
14.787	0.626	tINS	FF	2	R18C11[2][A]	test1/w002_6_s6/F
15.597	0.810	tNET	FF	2	R17C10[0][A]	test1/n552_s/I0
16.642	1.045	tINS	FF	1	R17C10[0][A]	test1/n552_s/COUT
16.642	0.000	tNET	FF	2	R17C10[0][B]	test1/n551_s/CIN
17.205	0.563	tINS	FF	2	R17C10[0][B]	test1/n551_s/SUM
18.015	0.810	tNET	FF	1	R18C9[2][A]	test1/w003_7_s4/I1
18.641	0.626	tINS	FF	1	R18C9[2][A]	test1/w003_7_s4/F
18.646	0.005	tNET	FF	1	R18C9[1][A]	test1/w003_7_s1/I3
19.468	0.822	tINS	FF	1	R18C9[1][A]	test1/w003_7_s1/F
19.474	0.005	tNET	FF	1	R18C9[3][B]	test1/w003_7_s0/I2
20.100	0.626	tINS	FF	2	R18C9[3][B]	test1/w003_7_s0/F
20.909	0.810	tNET	FF	2	R18C12[1][B]	test1/n669_1_s/I0
21.867	0.958	tINS	FF	1	R18C12[1][B]	test1/n669_1_s/COUT
21.867	0.000	tNET	FF	2	R18C12[2][A]	test1/n668_1_s/CIN
22.430	0.563	tINS	FF	1	R18C12[2][A]	test1/n668_1_s/SUM
23.235	0.804	tNET	FF	1	R17C13[2][A]	test1/w004_8_s2/I2
24.057	0.822	tINS	FF	2	R17C13[2][A]	test1/w004_8_s2/F
24.068	0.011	tNET	FF	1	R17C13[0][B]	test1/w004_8_s0/I2
24.890	0.822	tINS	FF	1	R17C13[0][B]	test1/w004_8_s0/F
26.025	1.135	tNET	FF	2	R18C14[2][A]	test1/n702_1_s/I0
27.019	0.994	tINS	FR	2	R18C14[2][A]	test1/n702_1_s/SUM
27.442	0.423	tNET	RR	1	R17C14[2][B]	test1/w005_8_s2/I1
28.474	1.032	tINS	RF	1	R17C14[2][B]	test1/w005_8_s2/F
29.278	0.804	tNET	FF	2	R17C15[2][A]	test1/n736_1_s/I0
30.261	0.983	tINS	FF	1	R17C15[2][A]	test1/n736_1_s/SUM
31.236	0.975	tNET	FF	1	R20C15[0][B]	test1/dac1/n21_s3/I0
32.262	1.026	tINS	FR	1	R20C15[0][B]	test1/dac1/n21_s3/F
32.681	0.419	tNET	RR	1	R20C14[1][B]	test1/dac1/n21_s0/I0
33.713	1.032	tINS	RF	1	R20C14[1][B]	test1/dac1/n21_s0/F
33.713	0.000	tNET	FF	1	R20C14[1][B]	test1/dac1/outshr_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cpuclk
20.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
22.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
23.484	1.396	tNET	RR	1	R20C14[1][B]	test1/dac1/outshr_8_s0/CLK
23.084	-0.400	tSu		1	R20C14[1][B]	test1/dac1/outshr_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	22
Arrival Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay	cell: 16.569, 54.812%; route: 13.201, 43.671%; tC2Q: 0.458, 1.516%
Required Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%

Path5

Path Summary:

Slack	-7.602
Data Arrival Time	30.686
Data Required Time	23.084
From	test1/toneA/toneout_s23
To	test1/dac1/outshr_7_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
2.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
3.484	1.396	tNET	RR	1	R13C16[1][A]	test1/toneA/toneout_s23/CLK
3.942	0.458	tC2Q	RF	6	R13C16[1][A]	test1/toneA/toneout_s23/Q
5.246	1.304	tNET	FF	1	R17C17[3][A]	test1/w001_6_s2/I0
5.872	0.626	tINS	FF	1	R17C17[3][A]	test1/w001_6_s2/F
7.007	1.135	tNET	FF	1	R16C16[0][B]	test1/w001_6_s1/I0
7.633	0.626	tINS	FF	2	R16C16[0][B]	test1/w001_6_s1/F
8.443	0.810	tNET	FF	1	R17C17[1][B]	test1/w001_6_s0/I2
9.265	0.822	tINS	FF	2	R17C17[1][B]	test1/w001_6_s0/F
9.761	0.496	tNET	FF	2	R18C17[0][A]	test1/n376_s/I0
10.464	0.703	tINS	FF	1	R18C17[0][A]	test1/n376_s/SUM
11.438	0.975	tNET	FF	1	R16C16[0][A]	test1/w002_6_s5/I1
12.064	0.626	tINS	FF	1	R16C16[0][A]	test1/w002_6_s5/F
12.070	0.005	tNET	FF	1	R16C16[1][A]	test1/w002_6_s2/I2
12.696	0.626	tINS	FF	3	R16C16[1][A]	test1/w002_6_s2/F
14.161	1.465	tNET	FF	1	R18C11[2][A]	test1/w002_6_s6/I3
14.787	0.626	tINS	FF	2	R18C11[2][A]	test1/w002_6_s6/F
15.597	0.810	tNET	FF	2	R17C10[0][A]	test1/n552_s/I0
16.642	1.045	tINS	FF	1	R17C10[0][A]	test1/n552_s/COUT
16.642	0.000	tNET	FF	2	R17C10[0][B]	test1/n551_s/CIN
17.205	0.563	tINS	FF	2	R17C10[0][B]	test1/n551_s/SUM
18.015	0.810	tNET	FF	1	R18C9[2][A]	test1/w003_7_s4/I1
18.641	0.626	tINS	FF	1	R18C9[2][A]	test1/w003_7_s4/F
18.646	0.005	tNET	FF	1	R18C9[1][A]	test1/w003_7_s1/I3
19.468	0.822	tINS	FF	1	R18C9[1][A]	test1/w003_7_s1/F
19.474	0.005	tNET	FF	1	R18C9[3][B]	test1/w003_7_s0/I2
20.100	0.626	tINS	FF	2	R18C9[3][B]	test1/w003_7_s0/F
20.909	0.810	tNET	FF	2	R18C12[1][B]	test1/n669_1_s/I0
21.903	0.994	tINS	FR	2	R18C12[1][B]	test1/n669_1_s/SUM
22.324	0.421	tNET	RR	1	R18C11[3][A]	test1/w004_7_s1/I1
23.146	0.822	tINS	RF	1	R18C11[3][A]	test1/w004_7_s1/F
23.951	0.804	tNET	FF	2	R18C14[1][B]	test1/n703_1_s/I0
24.945	0.994	tINS	FR	1	R18C14[1][B]	test1/n703_1_s/SUM
24.947	0.002	tNET	RR	1	R18C14[3][A]	test1/w005_7_s3/I1
26.046	1.099	tINS	RF	2	R18C14[3][A]	test1/w005_7_s3/F
26.855	0.810	tNET	FF	2	R17C15[1][B]	test1/n737_1_s/I0
27.838	0.983	tINS	FF	1	R17C15[1][B]	test1/n737_1_s/SUM
28.643	0.804	tNET	FF	1	R20C15[3][A]	test1/dac1/n22_s1/I1
29.445	0.802	tINS	FR	1	R20C15[3][A]	test1/dac1/n22_s1/F
29.864	0.419	tNET	RR	1	R21C15[2][A]	test1/dac1/n22_s0/I1
30.686	0.822	tINS	RF	1	R21C15[2][A]	test1/dac1/n22_s0/F
30.686	0.000	tNET	FF	1	R21C15[2][A]	test1/dac1/outshr_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cpuclk
20.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
22.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
23.484	1.396	tNET	RR	1	R21C15[2][A]	test1/dac1/outshr_7_s0/CLK
23.084	-0.400	tSu		1	R21C15[2][A]	test1/dac1/outshr_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	20
Arrival Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay	cell: 14.853, 54.603%; route: 11.890, 43.712%; tC2Q: 0.458, 1.685%
Required Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%

Path6

Path Summary:

Slack	-6.601
Data Arrival Time	29.686
Data Required Time	23.084
From	test1/toneA/toneout_s23
To	test1/dac1/outshr_6_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
2.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
3.484	1.396	tNET	RR	1	R13C16[1][A]	test1/toneA/toneout_s23/CLK
3.942	0.458	tC2Q	RF	6	R13C16[1][A]	test1/toneA/toneout_s23/Q
5.246	1.304	tNET	FF	1	R17C17[3][A]	test1/w001_6_s2/I0
5.872	0.626	tINS	FF	1	R17C17[3][A]	test1/w001_6_s2/F
7.007	1.135	tNET	FF	1	R16C16[0][B]	test1/w001_6_s1/I0
7.633	0.626	tINS	FF	2	R16C16[0][B]	test1/w001_6_s1/F
8.443	0.810	tNET	FF	1	R17C17[1][B]	test1/w001_6_s0/I2
9.265	0.822	tINS	FF	2	R17C17[1][B]	test1/w001_6_s0/F
9.761	0.496	tNET	FF	2	R18C17[0][A]	test1/n376_s/I0
10.464	0.703	tINS	FF	1	R18C17[0][A]	test1/n376_s/SUM
11.438	0.975	tNET	FF	1	R16C16[0][A]	test1/w002_6_s5/I1
12.064	0.626	tINS	FF	1	R16C16[0][A]	test1/w002_6_s5/F
12.070	0.005	tNET	FF	1	R16C16[1][A]	test1/w002_6_s2/I2
12.696	0.626	tINS	FF	3	R16C16[1][A]	test1/w002_6_s2/F
14.161	1.465	tNET	FF	1	R18C11[2][A]	test1/w002_6_s6/I3
14.787	0.626	tINS	FF	2	R18C11[2][A]	test1/w002_6_s6/F
15.597	0.810	tNET	FF	2	R17C10[0][A]	test1/n552_s/I0
16.300	0.703	tINS	FF	1	R17C10[0][A]	test1/n552_s/SUM
17.121	0.821	tNET	FF	1	R17C9[1][A]	test1/w003_6_s6/I1
17.943	0.822	tINS	FF	3	R17C9[1][A]	test1/w003_6_s6/F
18.758	0.815	tNET	FF	1	R18C9[0][B]	test1/w003_6_s0/I2
19.580	0.822	tINS	FF	1	R18C9[0][B]	test1/w003_6_s0/F
20.384	0.804	tNET	FF	2	R18C12[1][A]	test1/n670_1_s/I0
21.367	0.983	tINS	FF	2	R18C12[1][A]	test1/n670_1_s/SUM
21.862	0.495	tNET	FF	1	R18C14[3][B]	test1/w004_6_s6/I1
22.488	0.626	tINS	FF	1	R18C14[3][B]	test1/w004_6_s6/F
22.493	0.005	tNET	FF	2	R18C14[1][A]	test1/n704_1_s/I0
23.487	0.994	tINS	FR	1	R18C14[1][A]	test1/n704_1_s/SUM
23.906	0.419	tNET	RR	1	R18C15[2][A]	test1/w005_6_s4/I0
24.532	0.626	tINS	RF	2	R18C15[2][A]	test1/w005_6_s4/F
24.543	0.011	tNET	FF	1	R18C15[2][B]	test1/w005_6_s0/I2
25.365	0.822	tINS	FF	1	R18C15[2][B]	test1/w005_6_s0/F
25.855	0.490	tNET	FF	2	R17C15[1][A]	test1/n738_1_s/I0
26.838	0.983	tINS	FF	1	R17C15[1][A]	test1/n738_1_s/SUM
27.643	0.804	tNET	FF	1	R20C15[2][A]	test1/dac1/n23_s3/I1
28.445	0.802	tINS	FR	1	R20C15[2][A]	test1/dac1/n23_s3/F
28.864	0.419	tNET	RR	1	R21C15[1][A]	test1/dac1/n23_s0/I0
29.686	0.822	tINS	RF	1	R21C15[1][A]	test1/dac1/n23_s0/F
29.686	0.000	tNET	FF	1	R21C15[1][A]	test1/dac1/outshr_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cpuclk
20.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
22.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
23.484	1.396	tNET	RR	1	R21C15[1][A]	test1/dac1/outshr_6_s0/CLK
23.084	-0.400	tSu		1	R21C15[1][A]	test1/dac1/outshr_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay	cell: 13.660, 52.134%; route: 12.083, 46.116%; tC2Q: 0.458, 1.749%
Required Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%

Path7

Path Summary:

Slack	-3.578
Data Arrival Time	26.662
Data Required Time	23.084
From	test1/env1/env_amp_0_s0
To	test1/dac1/outshr_5_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
2.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
3.484	1.396	tNET	RR	1	R11C9[0][A]	test1/env1/env_amp_0_s0/CLK
3.942	0.458	tC2Q	RF	11	R11C9[0][A]	test1/env1/env_amp_0_s0/Q
5.750	1.807	tNET	FF	1	R17C17[3][B]	test1/ampA_0_s0/I1
6.572	0.822	tINS	FF	7	R17C17[3][B]	test1/ampA_0_s0/F
6.599	0.027	tNET	FF	1	R17C17[0][A]	test1/w001_5_s2/I0
7.631	1.032	tINS	FF	1	R17C17[0][A]	test1/w001_5_s2/F
8.436	0.804	tNET	FF	2	R18C18[0][B]	test1/n369_1_s/I0
9.419	0.983	tINS	FF	1	R18C18[0][B]	test1/n369_1_s/SUM
10.239	0.821	tNET	FF	1	R18C16[0][B]	test1/w002_5_s0/I2
11.061	0.822	tINS	FF	2	R18C16[0][B]	test1/w002_5_s0/F
12.541	1.480	tNET	FF	2	R18C10[0][B]	test1/n545_1_s/I0
13.535	0.994	tINS	FR	1	R18C10[0][B]	test1/n545_1_s/SUM
13.537	0.002	tNET	RR	1	R18C10[3][A]	test1/w003_5_s1/I1
14.636	1.099	tINS	RF	2	R18C10[3][A]	test1/w003_5_s1/F
15.467	0.831	tNET	FF	2	R18C12[0][B]	test1/n671_1_s/I0
16.461	0.994	tINS	FR	1	R18C12[0][B]	test1/n671_1_s/SUM
16.463	0.002	tNET	RR	1	R18C12[3][B]	test1/w004_5_s1/I1
17.562	1.099	tINS	RF	3	R18C12[3][B]	test1/w004_5_s1/F
18.057	0.496	tNET	FF	2	R18C14[0][B]	test1/n705_1_s/I0
19.040	0.983	tINS	FF	2	R18C14[0][B]	test1/n705_1_s/SUM
19.849	0.809	tNET	FF	1	R20C15[3][B]	test1/w005_5_s1/I1
20.948	1.099	tINS	FF	1	R20C15[3][B]	test1/w005_5_s1/F
21.752	0.804	tNET	FF	2	R17C15[0][B]	test1/n739_1_s/I0
22.735	0.983	tINS	FF	1	R17C15[0][B]	test1/n739_1_s/SUM
23.710	0.975	tNET	FF	1	R21C15[3][B]	test1/dac1/n24_s2/I0
24.742	1.032	tINS	FF	1	R21C15[3][B]	test1/dac1/n24_s2/F
25.563	0.821	tNET	FF	1	R20C15[1][B]	test1/dac1/n24_s0/I3
26.662	1.099	tINS	FF	1	R20C15[1][B]	test1/dac1/n24_s0/F
26.662	0.000	tNET	FF	1	R20C15[1][B]	test1/dac1/outshr_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cpuclk
20.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
22.088	2.088	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
23.484	1.396	tNET	RR	1	R20C15[1][B]	test1/dac1/outshr_5_s0/CLK
23.084	-0.400	tSu		1	R20C15[1][B]	test1/dac1/outshr_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	14
Arrival Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%
Arrival Data Path Delay	cell: 13.041, 56.265%; route: 9.679, 41.758%; tC2Q: 0.458, 1.977%
Required Clock Path Delay	cell: 2.088, 59.930%; route: 1.396, 40.070%

Path8

Path Summary:

Slack	-0.410
Data Arrival Time	21.234
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_0
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R16C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/CLK
14.318	0.458	tC2Q	FF	18	R16C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/Q
16.455	2.136	tNET	FF	1	R11C21[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_0/I0
17.554	1.099	tINS	FF	2	R11C21[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_0/F
19.497	1.944	tNET	FF	1	R11C8[3][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_0/I0
20.523	1.026	tINS	FR	1	R11C8[3][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_0/F
21.234	0.711	tNET	RR	1	BSRAM_R10[1]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_0/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R10[1]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_0/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_0
20.824	-0.174	tSu		1	BSRAM_R10[1]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_0

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 2.125, 28.816%; route: 4.791, 64.969%; tC2Q: 0.458, 6.215%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path9

Path Summary:

Slack	-0.309
Data Arrival Time	21.133
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R16C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/CLK
14.318	0.458	tC2Q	FF	18	R16C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/Q
16.455	2.136	tNET	FF	1	R11C21[1][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_4/I0
17.554	1.099	tINS	FF	2	R11C21[1][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_4/F
18.528	0.974	tNET	FF	1	R11C29[3][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_12/I0
19.589	1.061	tINS	FR	1	R11C29[3][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_12/F
21.133	1.544	tNET	RR	1	BSRAM_R10[8]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R10[8]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12
20.824	-0.174	tSu		1	BSRAM_R10[8]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_12

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 2.160, 29.700%; route: 4.654, 63.998%; tC2Q: 0.458, 6.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path10

Path Summary:

Slack	0.016
Data Arrival Time	20.808
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R18C28[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/CLK
14.318	0.458	tC2Q	FF	16	R18C28[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/Q
16.456	2.137	tNET	FF	1	R12C27[3]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_9/I2
17.231	0.775	tINS	FF	1	R12C27[3]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_9/F
17.730	0.500	tNET	FF	1	R12C27[2][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_18/I0
18.355	0.625	tINS	FR	1	R12C27[2][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_18/F
20.808	2.453	tNET	RR	1	BSRAM_R28[3]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R28[3]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18
20.824	-0.174	tSu		1	BSRAM_R28[3]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_18

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 1.400, 20.150%; route: 5.090, 73.254%; tC2Q: 0.458, 6.597%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path11

Path Summary:

Slack	0.134
Data Arrival Time	20.690
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_4
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R16C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/CLK
14.318	0.458	tC2Q	FF	18	R16C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/Q
16.455	2.136	tNET	FF	1	R11C21[1][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_4/I0
17.554	1.099	tINS	FF	2	R11C21[1][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_4/F
19.177	1.623	tNET	FF	1	R11C5[0][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_4/I0
19.979	0.802	tINS	FR	1	R11C5[0][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_4/F
20.690	0.711	tNET	RR	1	BSRAM_R10[0]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_4/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R10[0]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_4/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_4
20.824	-0.174	tSu		1	BSRAM_R10[0]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_4

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 1.901, 27.831%; route: 4.471, 65.459%; tC2Q: 0.458, 6.710%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path12

Path Summary:

Slack	0.188
Data Arrival Time	20.636
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_14_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_7
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R18C28[1][B]	svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/CLK
14.318	0.458	tC2Q	FF	16	R18C28[1][B]	svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q
15.831	1.513	tNET	FF	1	R12C28[3][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_7/I2
16.863	1.032	tINS	FF	2	R12C28[3][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_7/F
18.807	1.944	tNET	FF	1	R12C15[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_7/I0
19.432	0.625	tINS	FR	1	R12C15[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_7/F
20.636	1.205	tNET	RR	1	BSRAM_R28[4]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_7/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R28[4]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_7/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_7
20.824	-0.174	tSu		1	BSRAM_R28[4]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_7

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 1.657, 24.452%; route: 4.661, 68.784%; tC2Q: 0.458, 6.764%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path13

Path Summary:

Slack	0.492
Data Arrival Time	20.332
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_1
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R17C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/CLK
14.318	0.458	tC2Q	FF	16	R17C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q
16.459	2.141	tNET	FF	1	R12C21[0][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_1/I3
17.485	1.026	tINS	FR	2	R12C21[0][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_1/F
17.908	0.423	tNET	RR	1	R12C20[0][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_1/I0
18.710	0.802	tINS	RR	1	R12C20[0][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_1/F
20.332	1.622	tNET	RR	1	BSRAM_R28[6]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_1/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R28[6]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_1/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_1
20.824	-0.174	tSu		1	BSRAM_R28[6]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_1

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 1.828, 28.244%; route: 4.186, 64.674%; tC2Q: 0.458, 7.082%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path14

Path Summary:

Slack	0.531
Data Arrival Time	20.293
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_5
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R17C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/CLK
14.318	0.458	tC2Q	FF	16	R17C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q
15.815	1.497	tNET	FF	1	R12C28[1][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_5/I3
16.847	1.032	tINS	FF	2	R12C28[1][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_5/F
16.858	0.011	tNET	FF	1	R12C28[0][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_5/I0
17.919	1.061	tINS	FR	1	R12C28[0][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_5/F
20.293	2.374	tNET	RR	1	BSRAM_R28[5]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_5/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R28[5]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_5/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_5
20.824	-0.174	tSu		1	BSRAM_R28[5]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_5

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 2.093, 32.534%; route: 3.882, 60.342%; tC2Q: 0.458, 7.124%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path15

Path Summary:

Slack	0.881
Data Arrival Time	19.943
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_10
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R18C28[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/CLK
14.318	0.458	tC2Q	FF	16	R18C28[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/Q
16.457	2.139	tNET	FF	1	R12C27[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_2/I1
17.279	0.822	tINS	FF	2	R12C27[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_2/F
17.775	0.496	tNET	FF	1	R12C25[1][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_10/I0
18.400	0.625	tINS	FR	1	R12C25[1][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_10/F
19.943	1.544	tNET	RR	1	BSRAM_R10[4]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_10/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R10[4]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_10/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_10
20.824	-0.174	tSu		1	BSRAM_R10[4]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_10

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 1.447, 23.787%; route: 4.178, 68.679%; tC2Q: 0.458, 7.534%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path16

Path Summary:

Slack	0.918
Data Arrival Time	19.906
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_3
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R18C28[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/CLK
14.318	0.458	tC2Q	FF	16	R18C28[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/Q
16.284	1.966	tNET	FF	1	R12C26[2][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_3/I1
16.910	0.626	tINS	FF	2	R12C26[2][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_3/F
16.921	0.011	tNET	FF	1	R12C26[2][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_3/I0
17.947	1.026	tINS	FR	1	R12C26[2][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_3/F
19.906	1.959	tNET	RR	1	BSRAM_R28[9]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_3/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R28[9]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_3/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_3
20.824	-0.174	tSu		1	BSRAM_R28[9]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_3

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 1.652, 27.324%; route: 3.936, 65.096%; tC2Q: 0.458, 7.581%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path17

Path Summary:

Slack	0.920
Data Arrival Time	19.904
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R18C28[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/CLK
14.318	0.458	tC2Q	FF	16	R18C28[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/Q
16.284	1.966	tNET	FF	1	R12C26[3][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_8/I1
16.910	0.626	tINS	FF	2	R12C26[3][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_8/F
16.921	0.011	tNET	FF	1	R12C26[3][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_16/I0
17.947	1.026	tINS	FR	1	R12C26[3][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_16/F
19.904	1.957	tNET	RR	1	BSRAM_R28[11]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R28[11]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16
20.824	-0.174	tSu		1	BSRAM_R28[11]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_16

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 1.652, 27.331%; route: 3.934, 65.087%; tC2Q: 0.458, 7.583%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path18

Path Summary:

Slack	1.036
Data Arrival Time	19.789
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R16C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/CLK
14.318	0.458	tC2Q	FF	18	R16C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_12_s0/Q
16.455	2.136	tNET	FF	1	R11C21[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_0/I0
17.516	1.061	tINS	FR	2	R11C21[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_0/F
17.937	0.421	tNET	RR	1	R11C22[0][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_8/I0
18.998	1.061	tINS	RR	1	R11C22[0][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_8/F
19.789	0.791	tNET	RR	1	BSRAM_R10[6]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R10[6]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8
20.824	-0.174	tSu		1	BSRAM_R10[6]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_8

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 2.122, 35.792%; route: 3.348, 56.477%; tC2Q: 0.458, 7.731%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path19

Path Summary:

Slack	1.255
Data Arrival Time	19.569
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_17
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R18C28[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/CLK
14.318	0.458	tC2Q	FF	16	R18C28[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/Q
16.284	1.966	tNET	FF	1	R12C26[3][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_8/I1
16.910	0.626	tINS	FF	2	R12C26[3][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_8/F
16.921	0.011	tNET	FF	1	R12C26[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_17/I0
17.947	1.026	tINS	FR	1	R12C26[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_17/F
19.569	1.622	tNET	RR	1	BSRAM_R28[8]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_17/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R28[8]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_17/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_17
20.824	-0.174	tSu		1	BSRAM_R28[8]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_17

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 1.652, 28.937%; route: 3.599, 63.035%; tC2Q: 0.458, 8.028%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path20

Path Summary:

Slack	1.279
Data Arrival Time	19.545
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_14_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_15
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R18C28[1][B]	svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/CLK
14.318	0.458	tC2Q	FF	16	R18C28[1][B]	svo_hdmi_inst/svo_tcard/bramwraddr_14_s0/Q
15.831	1.513	tNET	FF	1	R12C28[3][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_7/I2
16.857	1.026	tINS	FR	2	R12C28[3][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_7/F
17.278	0.421	tNET	RR	1	R12C29[0][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_15/I0
18.339	1.061	tINS	RR	1	R12C29[0][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_15/F
19.545	1.206	tNET	RR	1	BSRAM_R10[9]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_15/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R10[9]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_15/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_15
20.824	-0.174	tSu		1	BSRAM_R10[9]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_15

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 2.087, 36.708%; route: 3.140, 55.230%; tC2Q: 0.458, 8.062%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path21

Path Summary:

Slack	1.283
Data Arrival Time	19.541
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_13
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R17C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/CLK
14.318	0.458	tC2Q	FF	16	R17C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q
15.815	1.497	tNET	FF	1	R12C28[1][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_5/I3
16.847	1.032	tINS	FF	2	R12C28[1][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_5/F
16.858	0.011	tNET	FF	1	R12C28[3][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_13/I0
17.919	1.061	tINS	FR	1	R12C28[3][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_13/F
19.541	1.622	tNET	RR	1	BSRAM_R10[2]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_13/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R10[2]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_13/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_13
20.824	-0.174	tSu		1	BSRAM_R10[2]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_13

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 2.093, 36.844%; route: 3.129, 55.088%; tC2Q: 0.458, 8.068%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path22

Path Summary:

Slack	1.284
Data Arrival Time	19.540
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_14
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R17C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/CLK
14.318	0.458	tC2Q	FF	16	R17C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q
15.815	1.497	tNET	FF	1	R12C28[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_6/I3
16.847	1.032	tINS	FF	2	R12C28[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_6/F
17.342	0.496	tNET	FF	1	R12C26[1][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_14/I0
17.967	0.625	tINS	FR	1	R12C26[1][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_14/F
19.540	1.573	tNET	RR	1	BSRAM_R28[7]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_14/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R28[7]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_14/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_14
20.824	-0.174	tSu		1	BSRAM_R28[7]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_14

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 1.657, 29.173%; route: 3.565, 62.758%; tC2Q: 0.458, 8.069%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path23

Path Summary:

Slack	1.323
Data Arrival Time	19.501
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_9
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R17C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/CLK
14.318	0.458	tC2Q	FF	16	R17C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q
16.459	2.141	tNET	FF	1	R12C21[0][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_1/I3
17.485	1.026	tINS	FR	2	R12C21[0][B]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_1/F
17.908	0.423	tNET	RR	1	R12C20[0][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_9/I0
18.710	0.802	tINS	RR	1	R12C20[0][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_9/F
19.501	0.791	tNET	RR	1	BSRAM_R10[5]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_9/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R10[5]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_9/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_9
20.824	-0.174	tSu		1	BSRAM_R10[5]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_9

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 1.828, 32.404%; route: 3.355, 59.472%; tC2Q: 0.458, 8.125%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path24

Path Summary:

Slack	1.337
Data Arrival Time	19.488
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_2
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R18C28[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/CLK
14.318	0.458	tC2Q	FF	16	R18C28[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_13_s0/Q
16.457	2.139	tNET	FF	1	R12C27[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_2/I1
17.279	0.822	tINS	FF	2	R12C27[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_2/F
17.290	0.011	tNET	FF	1	R12C27[0][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_2/I0
17.915	0.625	tINS	FR	1	R12C27[0][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_2/F
19.488	1.573	tNET	RR	1	BSRAM_R10[10]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_2/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R10[10]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_2/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_2
20.824	-0.174	tSu		1	BSRAM_R10[10]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_2

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 1.447, 25.713%; route: 3.722, 66.143%; tC2Q: 0.458, 8.144%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Path25

Path Summary:

Slack	1.432
Data Arrival Time	19.392
Data Required Time	20.824
From	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0
To	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_6
Launch Clk	cpuclk:[F]
Latch Clk	svo_hdmi_inst/svo_tcard/bram_aclock:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
12.314	2.314	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
13.860	1.546	tNET	FF	1	R17C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/CLK
14.318	0.458	tC2Q	FF	16	R17C27[1][A]	svo_hdmi_inst/svo_tcard/bramwraddr_15_s0/Q
15.815	1.497	tNET	FF	1	R12C28[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_6/I3
16.847	1.032	tINS	FF	2	R12C28[1][A]	svo_hdmi_inst/svo_tcard/your_instance_name/lut_inst_6/F
16.858	0.011	tNET	FF	1	R12C28[0][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_6/I0
17.483	0.625	tINS	FR	1	R12C28[0][B]	svo_hdmi_inst/svo_tcard/your_instance_name/gowin_add_lut2_BLKSELA_dpb_inst_6/F
19.392	1.910	tNET	RR	1	BSRAM_R28[10]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_6/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					svo_hdmi_inst/svo_tcard/bram_aclock
20.000	0.000	tCL	RR	23	R17C21[0][A]	svo_hdmi_inst/svo_tcard/bram_aclock_s0/Q
21.028	1.028	tNET	RR	1	BSRAM_R28[10]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_6/CLKA
20.998	-0.030	tUnc				svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_6
20.824	-0.174	tSu		1	BSRAM_R28[10]	svo_hdmi_inst/svo_tcard/your_instance_name/dpb_inst_6

Path Statistics:

Clock Skew	-2.832
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 2.314, 59.950%; route: 1.546, 40.050%
Arrival Data Path Delay	cell: 1.657, 29.950%; route: 3.417, 61.765%; tC2Q: 0.458, 8.284%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.028, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.183
Data Arrival Time	2.256
Data Required Time	2.440
From	test1/wng1/lfsr1/sfr_1_s0
To	test1/wng1/noiseout_s0
Launch Clk	test1/wng1/fsr_clk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					test1/wng1/fsr_clk
0.000	0.000	tCL	RR	16	R23C17[1][A]	test1/wng1/fsr_clk_s0/Q
0.966	0.966	tNET	RR	1	R22C17[0][A]	test1/wng1/lfsr1/sfr_1_s0/CLK
1.299	0.333	tC2Q	RR	2	R22C17[0][A]	test1/wng1/lfsr1/sfr_1_s0/Q
2.256	0.957	tNET	RR	1	R21C16[0][A]	test1/wng1/noiseout_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R21C16[0][A]	test1/wng1/noiseout_s0/CLK
2.440	0.030	tUnc				test1/wng1/noiseout_s0
2.440	0.000	tHld		1	R21C16[0][A]	test1/wng1/noiseout_s0

Path Statistics:

Clock Skew	1.444
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.966, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.957, 74.164%; tC2Q: 0.333, 25.836%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path2

Path Summary:

Slack	0.586
Data Arrival Time	1.111
Data Required Time	0.526
From	svo_hdmi_inst/svo_tmds_2/q_out_0_s0
To	svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s4
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R17C38[1][B]	svo_hdmi_inst/svo_tmds_2/q_out_0_s0/CLK
0.846	0.333	tC2Q	RR	1	R17C38[1][B]	svo_hdmi_inst/svo_tmds_2/q_out_0_s0/Q
1.111	0.265	tNET	RR	1	R15C38	svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s4/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C38	svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s4/CLK
0.526	0.012	tHld		1	R15C38	svo_hdmi_inst/svo_tmds_2/dout_buf2_0_s4

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.265, 44.283%; tC2Q: 0.333, 55.717%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path3

Path Summary:

Slack	0.598
Data Arrival Time	1.123
Data Required Time	0.526
From	svo_hdmi_inst/svo_term/oresetn_s0
To	svo_hdmi_inst/svo_term/p1_ypos_6_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R22C30[0][B]	svo_hdmi_inst/svo_term/oresetn_s0/CLK
0.846	0.333	tC2Q	RR	34	R22C30[0][B]	svo_hdmi_inst/svo_term/oresetn_s0/Q
1.123	0.277	tNET	RR	1	R22C29[0][B]	svo_hdmi_inst/svo_term/p1_ypos_6_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R22C29[0][B]	svo_hdmi_inst/svo_term/p1_ypos_6_s0/CLK
0.526	0.012	tHld		1	R22C29[0][B]	svo_hdmi_inst/svo_term/p1_ypos_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.277, 45.380%; tC2Q: 0.333, 54.620%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path4

Path Summary:

Slack	0.598
Data Arrival Time	1.123
Data Required Time	0.526
From	svo_hdmi_inst/svo_term/oresetn_s0
To	svo_hdmi_inst/svo_term/p1_ypos_12_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R22C30[0][B]	svo_hdmi_inst/svo_term/oresetn_s0/CLK
0.846	0.333	tC2Q	RR	34	R22C30[0][B]	svo_hdmi_inst/svo_term/oresetn_s0/Q
1.123	0.277	tNET	RR	1	R22C29[1][A]	svo_hdmi_inst/svo_term/p1_ypos_12_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R22C29[1][A]	svo_hdmi_inst/svo_term/p1_ypos_12_s0/CLK
0.526	0.012	tHld		1	R22C29[1][A]	svo_hdmi_inst/svo_term/p1_ypos_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.277, 45.380%; tC2Q: 0.333, 54.620%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path5

Path Summary:

Slack	0.708
Data Arrival Time	21.070
Data Required Time	20.362
From	svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1
To	svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
19.841	19.841					active clock edge time
19.841	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
20.362	0.191	tNET	FF	1	R20C25[0][A]	svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1/CLK
20.696	0.333	tC2Q	FR	2	R20C25[0][A]	svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1/Q
20.698	0.002	tNET	RR	1	R20C25[0][A]	svo_hdmi_inst/svo_tcard/grmode1/n68_s5/I3
21.070	0.372	tINS	RF	1	R20C25[0][A]	svo_hdmi_inst/svo_tcard/grmode1/n68_s5/F
21.070	0.000	tNET	FF	1	R20C25[0][A]	svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
19.841	19.841					active clock edge time
19.841	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
20.362	0.191	tNET	FF	1	R20C25[0][A]	svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1/CLK
20.362	0.000	tHld		1	R20C25[0][A]	svo_hdmi_inst/svo_tcard/grmode1/prescnibble_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.191, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.191, 100.000%

Path6

Path Summary:

Slack	0.708
Data Arrival Time	21.070
Data Required Time	20.362
From	svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0
To	svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
19.841	19.841					active clock edge time
19.841	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
20.362	0.191	tNET	FF	1	R21C22[0][A]	svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0/CLK
20.696	0.333	tC2Q	FR	2	R21C22[0][A]	svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0/Q
20.698	0.002	tNET	RR	1	R21C22[0][A]	svo_hdmi_inst/svo_tcard/grmode1/n199_s2/I2
21.070	0.372	tINS	RF	1	R21C22[0][A]	svo_hdmi_inst/svo_tcard/grmode1/n199_s2/F
21.070	0.000	tNET	FF	1	R21C22[0][A]	svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
19.841	19.841					active clock edge time
19.841	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
20.362	0.191	tNET	FF	1	R21C22[0][A]	svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0/CLK
20.362	0.000	tHld		1	R21C22[0][A]	svo_hdmi_inst/svo_tcard/grmode1/prescl_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.191, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.191, 100.000%

Path7

Path Summary:

Slack	0.708
Data Arrival Time	21.070
Data Required Time	20.362
From	svo_hdmi_inst/svo_tcard/grmode1/memcounth_11_s0
To	svo_hdmi_inst/svo_tcard/grmode1/memcounth_11_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
19.841	19.841					active clock edge time
19.841	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
20.362	0.191	tNET	FF	1	R21C25[1][A]	svo_hdmi_inst/svo_tcard/grmode1/memcounth_11_s0/CLK
20.696	0.333	tC2Q	FR	3	R21C25[1][A]	svo_hdmi_inst/svo_tcard/grmode1/memcounth_11_s0/Q
20.698	0.002	tNET	RR	1	R21C25[1][A]	svo_hdmi_inst/svo_tcard/grmode1/n142_s2/I3
21.070	0.372	tINS	RF	1	R21C25[1][A]	svo_hdmi_inst/svo_tcard/grmode1/n142_s2/F
21.070	0.000	tNET	FF	1	R21C25[1][A]	svo_hdmi_inst/svo_tcard/grmode1/memcounth_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
19.841	19.841					active clock edge time
19.841	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
20.362	0.191	tNET	FF	1	R21C25[1][A]	svo_hdmi_inst/svo_tcard/grmode1/memcounth_11_s0/CLK
20.362	0.000	tHld		1	R21C25[1][A]	svo_hdmi_inst/svo_tcard/grmode1/memcounth_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.191, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.191, 100.000%

Path8

Path Summary:

Slack	0.708
Data Arrival Time	21.070
Data Required Time	20.362
From	svo_hdmi_inst/svo_tcard/txtmode0/cursorcount_0_s1
To	svo_hdmi_inst/svo_tcard/txtmode0/cursorcount_0_s1
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
19.841	19.841					active clock edge time
19.841	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
20.362	0.191	tNET	FF	1	R14C27[1][A]	svo_hdmi_inst/svo_tcard/txtmode0/cursorcount_0_s1/CLK
20.696	0.333	tC2Q	FR	2	R14C27[1][A]	svo_hdmi_inst/svo_tcard/txtmode0/cursorcount_0_s1/Q
20.698	0.002	tNET	RR	1	R14C27[1][A]	svo_hdmi_inst/svo_tcard/txtmode0/n207_s3/I2
21.070	0.372	tINS	RF	1	R14C27[1][A]	svo_hdmi_inst/svo_tcard/txtmode0/n207_s3/F
21.070	0.000	tNET	FF	1	R14C27[1][A]	svo_hdmi_inst/svo_tcard/txtmode0/cursorcount_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
19.841	19.841					active clock edge time
19.841	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
20.362	0.191	tNET	FF	1	R14C27[1][A]	svo_hdmi_inst/svo_tcard/txtmode0/cursorcount_0_s1/CLK
20.362	0.000	tHld		1	R14C27[1][A]	svo_hdmi_inst/svo_tcard/txtmode0/cursorcount_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.191, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.191, 100.000%

Path9

Path Summary:

Slack	0.708
Data Arrival Time	13.382
Data Required Time	12.675
From	svo_hdmi_inst/svo_tcard/cled4_0_s2
To	svo_hdmi_inst/svo_tcard/cled4_0_s2
Launch Clk	cpuclk:[F]
Latch Clk	cpuclk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
11.542	1.542	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
12.675	1.133	tNET	FF	1	R22C20[1][A]	svo_hdmi_inst/svo_tcard/cled4_0_s2/CLK
13.008	0.333	tC2Q	FR	3	R22C20[1][A]	svo_hdmi_inst/svo_tcard/cled4_0_s2/Q
13.010	0.002	tNET	RR	1	R22C20[1][A]	svo_hdmi_inst/svo_tcard/n199_s5/I3
13.382	0.372	tINS	RF	1	R22C20[1][A]	svo_hdmi_inst/svo_tcard/n199_s5/F
13.382	0.000	tNET	FF	1	R22C20[1][A]	svo_hdmi_inst/svo_tcard/cled4_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
11.542	1.542	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
12.675	1.133	tNET	FF	1	R22C20[1][A]	svo_hdmi_inst/svo_tcard/cled4_0_s2/CLK
12.675	0.000	tHld		1	R22C20[1][A]	svo_hdmi_inst/svo_tcard/cled4_0_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.542, 57.649%; route: 1.133, 42.351%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.542, 57.649%; route: 1.133, 42.351%

Path10

Path Summary:

Slack	0.708
Data Arrival Time	13.382
Data Required Time	12.675
From	svo_hdmi_inst/svo_tcard/cled5_0_s2
To	svo_hdmi_inst/svo_tcard/cled5_0_s2
Launch Clk	cpuclk:[F]
Latch Clk	cpuclk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
11.542	1.542	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
12.675	1.133	tNET	FF	1	R17C23[0][A]	svo_hdmi_inst/svo_tcard/cled5_0_s2/CLK
13.008	0.333	tC2Q	FR	3	R17C23[0][A]	svo_hdmi_inst/svo_tcard/cled5_0_s2/Q
13.010	0.002	tNET	RR	1	R17C23[0][A]	svo_hdmi_inst/svo_tcard/n132_s5/I3
13.382	0.372	tINS	RF	1	R17C23[0][A]	svo_hdmi_inst/svo_tcard/n132_s5/F
13.382	0.000	tNET	FF	1	R17C23[0][A]	svo_hdmi_inst/svo_tcard/cled5_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
11.542	1.542	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
12.675	1.133	tNET	FF	1	R17C23[0][A]	svo_hdmi_inst/svo_tcard/cled5_0_s2/CLK
12.675	0.000	tHld		1	R17C23[0][A]	svo_hdmi_inst/svo_tcard/cled5_0_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.542, 57.649%; route: 1.133, 42.351%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.542, 57.649%; route: 1.133, 42.351%

Path11

Path Summary:

Slack	0.708
Data Arrival Time	13.382
Data Required Time	12.675
From	svo_hdmi_inst/svo_tcard/counter_0_s0
To	svo_hdmi_inst/svo_tcard/counter_0_s0
Launch Clk	cpuclk:[F]
Latch Clk	cpuclk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
11.542	1.542	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
12.675	1.133	tNET	FF	1	R6C18[0][A]	svo_hdmi_inst/svo_tcard/counter_0_s0/CLK
13.008	0.333	tC2Q	FR	2	R6C18[0][A]	svo_hdmi_inst/svo_tcard/counter_0_s0/Q
13.010	0.002	tNET	RR	1	R6C18[0][A]	svo_hdmi_inst/svo_tcard/n98_s2/I0
13.382	0.372	tINS	RF	1	R6C18[0][A]	svo_hdmi_inst/svo_tcard/n98_s2/F
13.382	0.000	tNET	FF	1	R6C18[0][A]	svo_hdmi_inst/svo_tcard/counter_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					cpuclk
10.000	0.000	tCL	FF	1	IOB23[A]	cpuclk_ibuf/I
11.542	1.542	tINS	FF	562	IOB23[A]	cpuclk_ibuf/O
12.675	1.133	tNET	FF	1	R6C18[0][A]	svo_hdmi_inst/svo_tcard/counter_0_s0/CLK
12.675	0.000	tHld		1	R6C18[0][A]	svo_hdmi_inst/svo_tcard/counter_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.542, 57.649%; route: 1.133, 42.351%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.542, 57.649%; route: 1.133, 42.351%

Path12

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	ps2_1/ps2timeout_0_s1
To	ps2_1/ps2timeout_0_s1
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R8C9[1][A]	ps2_1/ps2timeout_0_s1/CLK
2.743	0.333	tC2Q	RR	3	R8C9[1][A]	ps2_1/ps2timeout_0_s1/Q
2.745	0.002	tNET	RR	1	R8C9[1][A]	ps2_1/n141_s5/I2
3.117	0.372	tINS	RF	1	R8C9[1][A]	ps2_1/n141_s5/F
3.117	0.000	tNET	FF	1	R8C9[1][A]	ps2_1/ps2timeout_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R8C9[1][A]	ps2_1/ps2timeout_0_s1/CLK
2.410	0.000	tHld		1	R8C9[1][A]	ps2_1/ps2timeout_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path13

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	ps2_1/bitsreceived_3_s0
To	ps2_1/bitsreceived_3_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R7C9[0][A]	ps2_1/bitsreceived_3_s0/CLK
2.743	0.333	tC2Q	RR	2	R7C9[0][A]	ps2_1/bitsreceived_3_s0/Q
2.745	0.002	tNET	RR	1	R7C9[0][A]	ps2_1/n105_s1/I2
3.117	0.372	tINS	RF	1	R7C9[0][A]	ps2_1/n105_s1/F
3.117	0.000	tNET	FF	1	R7C9[0][A]	ps2_1/bitsreceived_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R7C9[0][A]	ps2_1/bitsreceived_3_s0/CLK
2.410	0.000	tHld		1	R7C9[0][A]	ps2_1/bitsreceived_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path14

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	test1/env1/clkdiv_0_s1
To	test1/env1/clkdiv_0_s1
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R9C11[0][A]	test1/env1/clkdiv_0_s1/CLK
2.743	0.333	tC2Q	RR	3	R9C11[0][A]	test1/env1/clkdiv_0_s1/Q
2.745	0.002	tNET	RR	1	R9C11[0][A]	test1/env1/n472_s5/I3
3.117	0.372	tINS	RF	1	R9C11[0][A]	test1/env1/n472_s5/F
3.117	0.000	tNET	FF	1	R9C11[0][A]	test1/env1/clkdiv_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R9C11[0][A]	test1/env1/clkdiv_0_s1/CLK
2.410	0.000	tHld		1	R9C11[0][A]	test1/env1/clkdiv_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path15

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	test1/wng1/divider_4_s0
To	test1/wng1/divider_4_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R23C18[0][A]	test1/wng1/divider_4_s0/CLK
2.743	0.333	tC2Q	RR	2	R23C18[0][A]	test1/wng1/divider_4_s0/Q
2.745	0.002	tNET	RR	1	R23C18[0][A]	test1/wng1/n59_s2/I1
3.117	0.372	tINS	RF	1	R23C18[0][A]	test1/wng1/n59_s2/F
3.117	0.000	tNET	FF	1	R23C18[0][A]	test1/wng1/divider_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R23C18[0][A]	test1/wng1/divider_4_s0/CLK
2.410	0.000	tHld		1	R23C18[0][A]	test1/wng1/divider_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path16

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	test1/wng1/clkdiv_2_s0
To	test1/wng1/clkdiv_2_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R22C16[1][A]	test1/wng1/clkdiv_2_s0/CLK
2.743	0.333	tC2Q	RR	3	R22C16[1][A]	test1/wng1/clkdiv_2_s0/Q
2.745	0.002	tNET	RR	1	R22C16[1][A]	test1/wng1/n84_s2/I2
3.117	0.372	tINS	RF	1	R22C16[1][A]	test1/wng1/n84_s2/F
3.117	0.000	tNET	FF	1	R22C16[1][A]	test1/wng1/clkdiv_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R22C16[1][A]	test1/wng1/clkdiv_2_s0/CLK
2.410	0.000	tHld		1	R22C16[1][A]	test1/wng1/clkdiv_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path17

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	test1/wng1/clkdiv_7_s0
To	test1/wng1/clkdiv_7_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R22C16[0][A]	test1/wng1/clkdiv_7_s0/CLK
2.743	0.333	tC2Q	RR	2	R22C16[0][A]	test1/wng1/clkdiv_7_s0/Q
2.745	0.002	tNET	RR	1	R22C16[0][A]	test1/wng1/n79_s2/I3
3.117	0.372	tINS	RF	1	R22C16[0][A]	test1/wng1/n79_s2/F
3.117	0.000	tNET	FF	1	R22C16[0][A]	test1/wng1/clkdiv_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R22C16[0][A]	test1/wng1/clkdiv_7_s0/CLK
2.410	0.000	tHld		1	R22C16[0][A]	test1/wng1/clkdiv_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path18

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	test1/toneC/clkdiv_2_s0
To	test1/toneC/clkdiv_2_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R22C10[1][A]	test1/toneC/clkdiv_2_s0/CLK
2.743	0.333	tC2Q	RR	3	R22C10[1][A]	test1/toneC/clkdiv_2_s0/Q
2.745	0.002	tNET	RR	1	R22C10[1][A]	test1/toneC/n112_s2/I2
3.117	0.372	tINS	RF	1	R22C10[1][A]	test1/toneC/n112_s2/F
3.117	0.000	tNET	FF	1	R22C10[1][A]	test1/toneC/clkdiv_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R22C10[1][A]	test1/toneC/clkdiv_2_s0/CLK
2.410	0.000	tHld		1	R22C10[1][A]	test1/toneC/clkdiv_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path19

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	test1/toneC/clkdiv_6_s0
To	test1/toneC/clkdiv_6_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R21C11[0][A]	test1/toneC/clkdiv_6_s0/CLK
2.743	0.333	tC2Q	RR	3	R21C11[0][A]	test1/toneC/clkdiv_6_s0/Q
2.745	0.002	tNET	RR	1	R21C11[0][A]	test1/toneC/n108_s4/I3
3.117	0.372	tINS	RF	1	R21C11[0][A]	test1/toneC/n108_s4/F
3.117	0.000	tNET	FF	1	R21C11[0][A]	test1/toneC/clkdiv_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R21C11[0][A]	test1/toneC/clkdiv_6_s0/CLK
2.410	0.000	tHld		1	R21C11[0][A]	test1/toneC/clkdiv_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path20

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	test1/toneB/divider_11_s0
To	test1/toneB/divider_11_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R14C17[0][A]	test1/toneB/divider_11_s0/CLK
2.743	0.333	tC2Q	RR	2	R14C17[0][A]	test1/toneB/divider_11_s0/Q
2.745	0.002	tNET	RR	1	R14C17[0][A]	test1/toneB/n72_s2/I3
3.117	0.372	tINS	RF	1	R14C17[0][A]	test1/toneB/n72_s2/F
3.117	0.000	tNET	FF	1	R14C17[0][A]	test1/toneB/divider_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R14C17[0][A]	test1/toneB/divider_11_s0/CLK
2.410	0.000	tHld		1	R14C17[0][A]	test1/toneB/divider_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path21

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	test1/toneB/clkdiv_3_s0
To	test1/toneB/clkdiv_3_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R13C17[1][A]	test1/toneB/clkdiv_3_s0/CLK
2.743	0.333	tC2Q	RR	2	R13C17[1][A]	test1/toneB/clkdiv_3_s0/Q
2.745	0.002	tNET	RR	1	R13C17[1][A]	test1/toneB/n111_s2/I3
3.117	0.372	tINS	RF	1	R13C17[1][A]	test1/toneB/n111_s2/F
3.117	0.000	tNET	FF	1	R13C17[1][A]	test1/toneB/clkdiv_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R13C17[1][A]	test1/toneB/clkdiv_3_s0/CLK
2.410	0.000	tHld		1	R13C17[1][A]	test1/toneB/clkdiv_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path22

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	test1/toneB/clkdiv_5_s0
To	test1/toneB/clkdiv_5_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R11C17[1][A]	test1/toneB/clkdiv_5_s0/CLK
2.743	0.333	tC2Q	RR	4	R11C17[1][A]	test1/toneB/clkdiv_5_s0/Q
2.745	0.002	tNET	RR	1	R11C17[1][A]	test1/toneB/n109_s2/I2
3.117	0.372	tINS	RF	1	R11C17[1][A]	test1/toneB/n109_s2/F
3.117	0.000	tNET	FF	1	R11C17[1][A]	test1/toneB/clkdiv_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R11C17[1][A]	test1/toneB/clkdiv_5_s0/CLK
2.410	0.000	tHld		1	R11C17[1][A]	test1/toneB/clkdiv_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path23

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	test1/toneA/divider_11_s0
To	test1/toneA/divider_11_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R12C13[0][A]	test1/toneA/divider_11_s0/CLK
2.743	0.333	tC2Q	RR	2	R12C13[0][A]	test1/toneA/divider_11_s0/Q
2.745	0.002	tNET	RR	1	R12C13[0][A]	test1/toneA/n72_s2/I3
3.117	0.372	tINS	RF	1	R12C13[0][A]	test1/toneA/n72_s2/F
3.117	0.000	tNET	FF	1	R12C13[0][A]	test1/toneA/divider_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R12C13[0][A]	test1/toneA/divider_11_s0/CLK
2.410	0.000	tHld		1	R12C13[0][A]	test1/toneA/divider_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path24

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	test1/toneA/clkdiv_3_s0
To	test1/toneA/clkdiv_3_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R9C15[1][A]	test1/toneA/clkdiv_3_s0/CLK
2.743	0.333	tC2Q	RR	2	R9C15[1][A]	test1/toneA/clkdiv_3_s0/Q
2.745	0.002	tNET	RR	1	R9C15[1][A]	test1/toneA/n111_s2/I3
3.117	0.372	tINS	RF	1	R9C15[1][A]	test1/toneA/n111_s2/F
3.117	0.000	tNET	FF	1	R9C15[1][A]	test1/toneA/clkdiv_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R9C15[1][A]	test1/toneA/clkdiv_3_s0/CLK
2.410	0.000	tHld		1	R9C15[1][A]	test1/toneA/clkdiv_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Path25

Path Summary:

Slack	0.708
Data Arrival Time	3.117
Data Required Time	2.410
From	test1/toneA/clkdiv_7_s0
To	test1/toneA/clkdiv_7_s0
Launch Clk	cpuclk:[R]
Latch Clk	cpuclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R11C14[0][A]	test1/toneA/clkdiv_7_s0/CLK
2.743	0.333	tC2Q	RR	2	R11C14[0][A]	test1/toneA/clkdiv_7_s0/Q
2.745	0.002	tNET	RR	1	R11C14[0][A]	test1/toneA/n107_s2/I3
3.117	0.372	tINS	RF	1	R11C14[0][A]	test1/toneA/n107_s2/F
3.117	0.000	tNET	FF	1	R11C14[0][A]	test1/toneA/clkdiv_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cpuclk
0.000	0.000	tCL	RR	1	IOB23[A]	cpuclk_ibuf/I
1.392	1.392	tINS	RR	562	IOB23[A]	cpuclk_ibuf/O
2.410	1.018	tNET	RR	1	R11C14[0][A]	test1/toneA/clkdiv_7_s0/CLK
2.410	0.000	tHld		1	R11C14[0][A]	test1/toneA/clkdiv_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 57.770%; route: 1.018, 42.230%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.975
Data Arrival Time	5.434
Data Required Time	6.409
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[0]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.346	1.315	tNET	FF	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.972	0.626	tINS	FF	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
5.434	2.462	tNET	FF	1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.968	3.968					active clock edge time
3.968	0.000					u_pll/rpll_inst/CLKOUT.default_gen_clk
6.362	2.394	tCL	FF	4	PLL_R	u_pll/rpll_inst/CLKOUT
6.484	0.121	tNET	FF	1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]/FCLK
6.454	-0.030	tUnc				svo_hdmi_inst/tmds_serdes[0]
6.409	-0.045	tSu		1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew	1.943
Setup Relationship	3.968
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.626, 12.875%; route: 3.778, 77.698%; tC2Q: 0.458, 9.427%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.121, 100.000%

Path2

Path Summary:

Slack	0.975
Data Arrival Time	5.434
Data Required Time	6.409
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[1]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.346	1.315	tNET	FF	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.972	0.626	tINS	FF	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
5.434	2.462	tNET	FF	1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.968	3.968					active clock edge time
3.968	0.000					u_pll/rpll_inst/CLKOUT.default_gen_clk
6.362	2.394	tCL	FF	4	PLL_R	u_pll/rpll_inst/CLKOUT
6.484	0.121	tNET	FF	1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]/FCLK
6.454	-0.030	tUnc				svo_hdmi_inst/tmds_serdes[1]
6.409	-0.045	tSu		1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew	1.943
Setup Relationship	3.968
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.626, 12.875%; route: 3.778, 77.698%; tC2Q: 0.458, 9.427%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.121, 100.000%

Path3

Path Summary:

Slack	0.975
Data Arrival Time	5.434
Data Required Time	6.409
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[2]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.346	1.315	tNET	FF	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.972	0.626	tINS	FF	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
5.434	2.462	tNET	FF	1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.968	3.968					active clock edge time
3.968	0.000					u_pll/rpll_inst/CLKOUT.default_gen_clk
6.362	2.394	tCL	FF	4	PLL_R	u_pll/rpll_inst/CLKOUT
6.484	0.121	tNET	FF	1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]/FCLK
6.454	-0.030	tUnc				svo_hdmi_inst/tmds_serdes[2]
6.409	-0.045	tSu		1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew	1.943
Setup Relationship	3.968
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.626, 12.875%; route: 3.778, 77.698%; tC2Q: 0.458, 9.427%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.121, 100.000%

Path4

Path Summary:

Slack	4.936
Data Arrival Time	5.434
Data Required Time	10.370
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[2]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.346	1.315	tNET	FF	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.972	0.626	tINS	FF	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
5.434	2.462	tNET	FF	1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.936	7.936					active clock edge time
7.936	0.000					u_pll/rpll_inst/CLKOUT.default_gen_clk
10.330	2.394	tCL	RR	4	PLL_R	u_pll/rpll_inst/CLKOUT
10.445	0.115	tNET	RR	1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]/FCLK
10.415	-0.030	tUnc				svo_hdmi_inst/tmds_serdes[2]
10.370	-0.045	tSu		1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew	1.937
Setup Relationship	7.936
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.626, 12.875%; route: 3.778, 77.698%; tC2Q: 0.458, 9.427%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.115, 100.000%

Path5

Path Summary:

Slack	4.936
Data Arrival Time	5.434
Data Required Time	10.370
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[1]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.346	1.315	tNET	FF	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.972	0.626	tINS	FF	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
5.434	2.462	tNET	FF	1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.936	7.936					active clock edge time
7.936	0.000					u_pll/rpll_inst/CLKOUT.default_gen_clk
10.330	2.394	tCL	RR	4	PLL_R	u_pll/rpll_inst/CLKOUT
10.445	0.115	tNET	RR	1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]/FCLK
10.415	-0.030	tUnc				svo_hdmi_inst/tmds_serdes[1]
10.370	-0.045	tSu		1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew	1.937
Setup Relationship	7.936
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.626, 12.875%; route: 3.778, 77.698%; tC2Q: 0.458, 9.427%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.115, 100.000%

Path6

Path Summary:

Slack	4.936
Data Arrival Time	5.434
Data Required Time	10.370
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[0]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.346	1.315	tNET	FF	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.972	0.626	tINS	FF	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
5.434	2.462	tNET	FF	1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.936	7.936					active clock edge time
7.936	0.000					u_pll/rpll_inst/CLKOUT.default_gen_clk
10.330	2.394	tCL	RR	4	PLL_R	u_pll/rpll_inst/CLKOUT
10.445	0.115	tNET	RR	1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]/FCLK
10.415	-0.030	tUnc				svo_hdmi_inst/tmds_serdes[0]
10.370	-0.045	tSu		1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew	1.937
Setup Relationship	7.936
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.626, 12.875%; route: 3.778, 77.698%; tC2Q: 0.458, 9.427%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.115, 100.000%

Path7

Path Summary:

Slack	34.775
Data Arrival Time	5.434
Data Required Time	40.210
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[2]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.346	1.315	tNET	FF	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.972	0.626	tINS	FF	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
5.434	2.462	tNET	FF	1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]/PCLK
40.210	-0.045	tSu		1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.626, 12.875%; route: 3.778, 77.698%; tC2Q: 0.458, 9.427%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path8

Path Summary:

Slack	34.775
Data Arrival Time	5.434
Data Required Time	40.210
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[1]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.346	1.315	tNET	FF	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.972	0.626	tINS	FF	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
5.434	2.462	tNET	FF	1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]/PCLK
40.210	-0.045	tSu		1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.626, 12.875%; route: 3.778, 77.698%; tC2Q: 0.458, 9.427%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path9

Path Summary:

Slack	34.775
Data Arrival Time	5.434
Data Required Time	40.210
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[0]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.346	1.315	tNET	FF	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.972	0.626	tINS	FF	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
5.434	2.462	tNET	FF	1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]/PCLK
40.210	-0.045	tSu		1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.626, 12.875%; route: 3.778, 77.698%; tC2Q: 0.458, 9.427%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.114
Data Arrival Time	3.635
Data Required Time	2.521
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[2]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.687	0.840	tNET	RR	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.072	0.385	tINS	RR	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
3.635	1.564	tNET	RR	1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_pll/rpll_inst/CLKOUT.default_gen_clk
2.394	2.394	tCL	RR	4	PLL_R	u_pll/rpll_inst/CLKOUT
2.478	0.085	tNET	RR	1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]/FCLK
2.508	0.030	tUnc				svo_hdmi_inst/tmds_serdes[2]
2.521	0.012	tHld		1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew	1.965
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.385, 12.331%; route: 2.404, 76.993%; tC2Q: 0.333, 10.676%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.085, 100.000%

Path2

Path Summary:

Slack	1.114
Data Arrival Time	3.635
Data Required Time	2.521
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[1]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.687	0.840	tNET	RR	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.072	0.385	tINS	RR	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
3.635	1.564	tNET	RR	1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_pll/rpll_inst/CLKOUT.default_gen_clk
2.394	2.394	tCL	RR	4	PLL_R	u_pll/rpll_inst/CLKOUT
2.478	0.085	tNET	RR	1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]/FCLK
2.508	0.030	tUnc				svo_hdmi_inst/tmds_serdes[1]
2.521	0.012	tHld		1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew	1.965
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.385, 12.331%; route: 2.404, 76.993%; tC2Q: 0.333, 10.676%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.085, 100.000%

Path3

Path Summary:

Slack	1.114
Data Arrival Time	3.635
Data Required Time	2.521
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[0]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_pll/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.687	0.840	tNET	RR	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.072	0.385	tINS	RR	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
3.635	1.564	tNET	RR	1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_pll/rpll_inst/CLKOUT.default_gen_clk
2.394	2.394	tCL	RR	4	PLL_R	u_pll/rpll_inst/CLKOUT
2.478	0.085	tNET	RR	1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]/FCLK
2.508	0.030	tUnc				svo_hdmi_inst/tmds_serdes[0]
2.521	0.012	tHld		1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew	1.965
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.385, 12.331%; route: 2.404, 76.993%; tC2Q: 0.333, 10.676%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.085, 100.000%

Path4

Path Summary:

Slack	3.110
Data Arrival Time	3.635
Data Required Time	0.526
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[0]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.687	0.840	tNET	RR	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.072	0.385	tINS	RR	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
3.635	1.564	tNET	RR	1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]/PCLK
0.526	0.012	tHld		1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.385, 12.331%; route: 2.404, 76.993%; tC2Q: 0.333, 10.676%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path5

Path Summary:

Slack	3.110
Data Arrival Time	3.635
Data Required Time	0.526
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[1]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.687	0.840	tNET	RR	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.072	0.385	tINS	RR	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
3.635	1.564	tNET	RR	1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]/PCLK
0.526	0.012	tHld		1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.385, 12.331%; route: 2.404, 76.993%; tC2Q: 0.333, 10.676%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path6

Path Summary:

Slack	3.110
Data Arrival Time	3.635
Data Required Time	0.526
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[2]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.687	0.840	tNET	RR	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.072	0.385	tINS	RR	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
3.635	1.564	tNET	RR	1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]/PCLK
0.526	0.012	tHld		1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.385, 12.331%; route: 2.404, 76.993%; tC2Q: 0.333, 10.676%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path7

Path Summary:

Slack	5.077
Data Arrival Time	3.635
Data Required Time	-1.441
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[0]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.687	0.840	tNET	RR	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.072	0.385	tINS	RR	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
3.635	1.564	tNET	RR	1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-3.968	-3.968					active clock edge time
-3.968	0.000					u_pll/rpll_inst/CLKOUT.default_gen_clk
-1.574	2.394	tCL	FF	4	PLL_R	u_pll/rpll_inst/CLKOUT
-1.484	0.090	tNET	FF	1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]/FCLK
-1.454	0.030	tUnc				svo_hdmi_inst/tmds_serdes[0]
-1.441	0.012	tHld		1	IOT41[A]	svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew	1.971
Hold Relationship	-3.968
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.385, 12.331%; route: 2.404, 76.993%; tC2Q: 0.333, 10.676%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.090, 100.000%

Path8

Path Summary:

Slack	5.077
Data Arrival Time	3.635
Data Required Time	-1.441
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[1]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.687	0.840	tNET	RR	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.072	0.385	tINS	RR	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
3.635	1.564	tNET	RR	1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-3.968	-3.968					active clock edge time
-3.968	0.000					u_pll/rpll_inst/CLKOUT.default_gen_clk
-1.574	2.394	tCL	FF	4	PLL_R	u_pll/rpll_inst/CLKOUT
-1.484	0.090	tNET	FF	1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]/FCLK
-1.454	0.030	tUnc				svo_hdmi_inst/tmds_serdes[1]
-1.441	0.012	tHld		1	IOT39[A]	svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew	1.971
Hold Relationship	-3.968
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.385, 12.331%; route: 2.404, 76.993%; tC2Q: 0.333, 10.676%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.090, 100.000%

Path9

Path Summary:

Slack	5.077
Data Arrival Time	3.635
Data Required Time	-1.441
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[2]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_pll/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	509	TOPSIDE[0]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	7	R15C34[0][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.687	0.840	tNET	RR	1	R18C36[1][B]	svo_hdmi_inst/n147_s1/I1
2.072	0.385	tINS	RR	96	R18C36[1][B]	svo_hdmi_inst/n147_s1/F
3.635	1.564	tNET	RR	1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-3.968	-3.968					active clock edge time
-3.968	0.000					u_pll/rpll_inst/CLKOUT.default_gen_clk
-1.574	2.394	tCL	FF	4	PLL_R	u_pll/rpll_inst/CLKOUT
-1.484	0.090	tNET	FF	1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]/FCLK
-1.454	0.030	tUnc				svo_hdmi_inst/tmds_serdes[2]
-1.441	0.012	tHld		1	IOT38[A]	svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew	1.971
Hold Relationship	-3.968
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.385, 12.331%; route: 2.404, 76.993%; tC2Q: 0.333, 10.676%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.090, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	7.300
Actual Width:	8.550
Required Width:	1.250
Type:	Low Pulse Width
Clock:	cpuclk
Objects:	spi_1/divider_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cpuclk
10.000	0.000	tCL	FF	cpuclk_ibuf/I
12.314	2.314	tINS	FF	cpuclk_ibuf/O
13.860	1.546	tNET	FF	spi_1/divider_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			cpuclk
20.000	0.000	tCL	RR	cpuclk_ibuf/I
21.392	1.392	tINS	RR	cpuclk_ibuf/O
22.410	1.018	tNET	RR	spi_1/divider_12_s0/CLK

MPW2

MPW Summary:

Slack:	7.300
Actual Width:	8.550
Required Width:	1.250
Type:	Low Pulse Width
Clock:	cpuclk
Objects:	spi_1/divider_10_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cpuclk
10.000	0.000	tCL	FF	cpuclk_ibuf/I
12.314	2.314	tINS	FF	cpuclk_ibuf/O
13.860	1.546	tNET	FF	spi_1/divider_10_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			cpuclk
20.000	0.000	tCL	RR	cpuclk_ibuf/I
21.392	1.392	tINS	RR	cpuclk_ibuf/O
22.410	1.018	tNET	RR	spi_1/divider_10_s0/CLK

MPW3

MPW Summary:

Slack:	7.300
Actual Width:	8.550
Required Width:	1.250
Type:	Low Pulse Width
Clock:	cpuclk
Objects:	spi_1/divider_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cpuclk
10.000	0.000	tCL	FF	cpuclk_ibuf/I
12.314	2.314	tINS	FF	cpuclk_ibuf/O
13.860	1.546	tNET	FF	spi_1/divider_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			cpuclk
20.000	0.000	tCL	RR	cpuclk_ibuf/I
21.392	1.392	tINS	RR	cpuclk_ibuf/O
22.410	1.018	tNET	RR	spi_1/divider_6_s0/CLK

MPW4

MPW Summary:

Slack:	7.300
Actual Width:	8.550
Required Width:	1.250
Type:	Low Pulse Width
Clock:	cpuclk
Objects:	spi_1/disk_sck_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cpuclk
10.000	0.000	tCL	FF	cpuclk_ibuf/I
12.314	2.314	tINS	FF	cpuclk_ibuf/O
13.860	1.546	tNET	FF	spi_1/disk_sck_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			cpuclk
20.000	0.000	tCL	RR	cpuclk_ibuf/I
21.392	1.392	tINS	RR	cpuclk_ibuf/O
22.410	1.018	tNET	RR	spi_1/disk_sck_s0/CLK

MPW5

MPW Summary:

Slack:	7.300
Actual Width:	8.550
Required Width:	1.250
Type:	Low Pulse Width
Clock:	cpuclk
Objects:	spi_1/data_rx_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cpuclk
10.000	0.000	tCL	FF	cpuclk_ibuf/I
12.314	2.314	tINS	FF	cpuclk_ibuf/O
13.860	1.546	tNET	FF	spi_1/data_rx_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			cpuclk
20.000	0.000	tCL	RR	cpuclk_ibuf/I
21.392	1.392	tINS	RR	cpuclk_ibuf/O
22.410	1.018	tNET	RR	spi_1/data_rx_1_s0/CLK

MPW6

MPW Summary:

Slack:	7.300
Actual Width:	8.550
Required Width:	1.250
Type:	Low Pulse Width
Clock:	cpuclk
Objects:	serial_1/txdata_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cpuclk
10.000	0.000	tCL	FF	cpuclk_ibuf/I
12.314	2.314	tINS	FF	cpuclk_ibuf/O
13.860	1.546	tNET	FF	serial_1/txdata_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			cpuclk
20.000	0.000	tCL	RR	cpuclk_ibuf/I
21.392	1.392	tINS	RR	cpuclk_ibuf/O
22.410	1.018	tNET	RR	serial_1/txdata_1_s0/CLK

MPW7

MPW Summary:

Slack:	7.300
Actual Width:	8.550
Required Width:	1.250
Type:	Low Pulse Width
Clock:	cpuclk
Objects:	test1/r0_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cpuclk
10.000	0.000	tCL	FF	cpuclk_ibuf/I
12.314	2.314	tINS	FF	cpuclk_ibuf/O
13.860	1.546	tNET	FF	test1/r0_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			cpuclk
20.000	0.000	tCL	RR	cpuclk_ibuf/I
21.392	1.392	tINS	RR	cpuclk_ibuf/O
22.410	1.018	tNET	RR	test1/r0_4_s0/CLK

MPW8

MPW Summary:

Slack:	7.300
Actual Width:	8.550
Required Width:	1.250
Type:	Low Pulse Width
Clock:	cpuclk
Objects:	test1/toneB/divider_11_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cpuclk
10.000	0.000	tCL	FF	cpuclk_ibuf/I
12.314	2.314	tINS	FF	cpuclk_ibuf/O
13.860	1.546	tNET	FF	test1/toneB/divider_11_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			cpuclk
20.000	0.000	tCL	RR	cpuclk_ibuf/I
21.392	1.392	tINS	RR	cpuclk_ibuf/O
22.410	1.018	tNET	RR	test1/toneB/divider_11_s0/CLK

MPW9

MPW Summary:

Slack:	7.300
Actual Width:	8.550
Required Width:	1.250
Type:	Low Pulse Width
Clock:	cpuclk
Objects:	svo_hdmi_inst/svo_tcard/bramwraddr_10_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cpuclk
10.000	0.000	tCL	FF	cpuclk_ibuf/I
12.314	2.314	tINS	FF	cpuclk_ibuf/O
13.860	1.546	tNET	FF	svo_hdmi_inst/svo_tcard/bramwraddr_10_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			cpuclk
20.000	0.000	tCL	RR	cpuclk_ibuf/I
21.392	1.392	tINS	RR	cpuclk_ibuf/O
22.410	1.018	tNET	RR	svo_hdmi_inst/svo_tcard/bramwraddr_10_s0/CLK

MPW10

MPW Summary:

Slack:	7.300
Actual Width:	8.550
Required Width:	1.250
Type:	Low Pulse Width
Clock:	cpuclk
Objects:	svo_hdmi_inst/svo_tcard/bramwraddr_11_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cpuclk
10.000	0.000	tCL	FF	cpuclk_ibuf/I
12.314	2.314	tINS	FF	cpuclk_ibuf/O
13.860	1.546	tNET	FF	svo_hdmi_inst/svo_tcard/bramwraddr_11_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			cpuclk
20.000	0.000	tCL	RR	cpuclk_ibuf/I
21.392	1.392	tINS	RR	cpuclk_ibuf/O
22.410	1.018	tNET	RR	svo_hdmi_inst/svo_tcard/bramwraddr_11_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
562	cpuclk_d	-12.499	1.546
509	clk_p	0.975	0.659
96	n147_5	0.975	2.947
57	n1716_6	14.508	4.403
56	pixel_fifo_rdaddr[2]	27.101	2.169
40	dff_q_7	10.782	1.818
39	n169_7	35.371	1.497
39	n169_5	32.902	1.521
35	n1757_12	12.375	2.961
34	oresetn	35.707	1.321

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R8C12	87.50%
R11C16	87.50%
R13C32	83.33%
R12C11	83.33%
R14C22	81.94%
R14C23	81.94%
R13C24	81.94%
R23C31	80.56%
R21C23	80.56%
R18C26	80.56%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk_osc -period 37.037 -waveform {0 18.518} [get_ports {clk}]